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PDF TDA8793HL Data sheet ( Hoja de datos )
| Número de pieza | TDA8793HL | |
| Descripción | 8-bit/ low-power/ 3 V/ 100 Msps Analog-to-Digital Converter ADC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TDA8793HL (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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INTEGRATED CIRCUITS
DATA SHEET
TDA8793
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
Preliminary specification
Supersedes data of 1998 May 14
File under Integrated Circuits, IC02
1999 Oct 06
1 page  
Philips Semiconductors
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
Preliminary specification
TDA8793
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
VCCD
VCCO
∆VCC
VINP, INN
IO
Tstg
Tamb
Tj
PARAMETER
analog supply voltage
digital supply voltage
output stages supply voltage
supply voltage differences between
VCCA and VCCD
VCCO and VCCD
VCCA and VCCO
input voltage range
output current
storage temperature
ambient temperature
junction temperature
CONDITIONS
referenced to AGND
MIN.
−0.3
−0.3
−0.3
MAX.
+7.0
+7.0
+7.0
UNIT
V
V
V
−1.0 +1.0 V
−1.0 +1.0 V
−1.0 +1.0 V
−0.3 +7.0 V
− 10 mA
−55
+150
°C
0 70 °C
− − °C
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
in free air
VALUE
94
UNIT
K/W
1999 Oct 06
5
5 Page 
Philips Semiconductors
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
8
handbook, halfpage
EB
(bits)
7
FCE422
6
5
1.15 1.25 1.35 1.45
VREFIN (V)
Typical values measured at VCCA = VCCD = VCCO = 3.0 V,
fCLK = 100 MHz, Tamb = 25 °C and single-ended input.
Fig.7 Effective bits as a function of VREFIN
reference input voltage.
Preliminary specification
TDA8793
handbook, full pagewidth
CLK
tCPH
tCPL
sample N
sample N + 1 sample N + 2
HIGH
50 %
LOW
Vl
DATA
D0 to D7
tds
DATA
N−2
DATA
N−1
td
th
DATA
N
DATA
N+1
HIGH
50 %
LOW
MGR018
1999 Oct 06
Fig.8 Timing diagram.
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet TDA8793HL.PDF ] | |
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