PDF TDA8784H Data sheet ( Hoja de datos )

Número de pieza	TDA8784H
Descripción	18 Msps/ 10-bit analog-to-digital interface for CCD cameras
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA8784 18 Msps, 10-bit analog-to-digital interface for CCD cameras Product speciﬁcation Supersedes data of 1998 Aug 05 File under Integrated Circuits, IC02 1999 Sep 21 1 page Philips Semiconductors 18 Msps, 10-bit analog-to-digital interface for CCD cameras Product speciﬁcation TDA8784 PINNING SYMBOL PIN DESCRIPTION CLPOB 1 clamp pulse input at optical black AGND4 2 analog ground 4 OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface) AMPOUT 4 CDS ampliﬁer output (ﬁxed gain = 6 dB) AGND1 5 analog ground 1 VCCA1 AGCOUT 6 analog supply voltage 1 7 AGC ampliﬁer signal output CPCDS 8 clamp storage capacitor pin AGND5 9 analog ground 5 ADCIN 10 ADC analog signal input from AGCOUT via a short circuit CLPADC Vref 11 clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground) 12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or shorted to ground via a capacitor) DACOUT 13 DAC output for ADC clamp level AGND2 14 analog ground 2 VCCA2 VRB VRT DEC1 15 analog supply voltage 2 16 ADC reference voltage (BOTTOM) code 0 17 ADC reference voltage (TOP) code 1023 18 decoupling 1 (decoupled to ground via a capacitor) AGND6 19 analog ground 6 SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off; additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode per block and edge pulse control); see Table 1 SCLK 21 serial clock input for the control DACs and their serial interface; see Table 1 SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1 STDBY 23 standby control pin (active HIGH); all the output bits are logic 0 when standby is enabled VCCD1 DGND1 24 digital supply voltage 1 25 digital ground 1 D0 26 ADC digital output 0 (LSB) D1 27 ADC digital output 1 D2 28 ADC digital output 2 D3 29 ADC digital output 3 D4 30 ADC digital output 4 D5 31 ADC digital output 5 D6 32 ADC digital output 6 D7 33 ADC digital output 7 D8 34 ADC digital output 8 D9 35 ADC digital output 9 (MSB) OGND 36 digital output ground VCCO 37 digital output supply voltage 1999 Sep 21 5 5 Page Philips Semiconductors 18 Msps, 10-bit analog-to-digital interface for CCD cameras Product speciﬁcation TDA8784 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ZOFDOUT additional 8-bit control DAC (OFD) output impedance IOFDOUT OFD output current drive ADC clamp control DAC (see Fig.8) VDACOUT(p-p) ADC clamp 10-bit control DAC output voltage (peak-to-peak value) VDACOUT DC output voltage ZDACOUT IDACOUT OFELOOP ADC clamp control DAC output impedance DAC output current drive maximum offset error of DAC + ADC clamp loop static code 0 code 1023 static code 0 code 1023 − 2000 − Ω − − 50 µA − 1−V − 1.5 − V − 2.5 − V − − 250 Ω − − 50 µA − ±5 − LSB − ±5 − LSB Digital outputs (fCLK = 18 MHz; CL = 20 pF) VOH HIGH-level output voltage IOH = −1 mA VOL LOW-level output voltage IOL = 1 mA IOZ output current in 3-state mode 0 V < Vo < VCCO to(h) output hold time see Fig.5 to(d) output delay time Ci = 20 pF; VCCO = 5 V Ci = 10 pF Ci = 20 pF; VCCO = 3 V Ci = 10 pF Ci = 20 pF; VCCO = 2.5 V Ci = 10 pF Serial interface VCCO − 0.5 0 −20 8 − − − − − − − − − − 17 15 20 17 22 18 VCCO 0.5 +20 − 23 21 29 25 33 28 V V µA ns ns ns ns ns ns ns fSCLK(max) maximum frequency of serial interface 5 − − MHz Note 1. Noise measurement at ADC outputs: the coupling capacitor at the input is connected to ground, so that only the noise contribution of the front-end is evaluated. The front-end operates at 18 Mpix with a line of 1024 pixels. The first 40 are used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels. The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise is taken into account as no signal is input. 1999 Sep 21 11 11 Page

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