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PDF TDA8763A Data sheet ( Hoja de datos )
| Número de pieza | TDA8763A | |
| Descripción | 10-bit high-speed low-power ADC | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8763A
10-bit high-speed low-power ADC
Product specification
Supersedes data of 1997 Feb 07
File under Integrated Circuits, IC02
1999 Jan 06
1 page  
Philips Semiconductors
10-bit high-speed low-power ADC
Product specification
TDA8763A
PINNING
SYMBOL PIN
DESCRIPTION
CLK 1 clock input
TC 2 twos complement input (active LOW)
VCCA
AGND
3 analog supply voltage (+5 V)
4 analog ground
n.c. 5 not connected
VRB 6 reference voltage BOTTOM input
VRM 7 reference voltage MIDDLE input
VI 8 analog input voltage
VRT 9 reference voltage TOP input
OE 10 output enable input (CMOS level
input, active LOW)
VCCD2
DGND2
11 digital supply voltage 2 (+5 V)
12 digital ground 2
VCCO
13 supply voltage for output stages
(3 to 5 V)
OGND
14 output ground
n.c. 15 not connected
D0 16 data output; bit 0 (LSB)
D1 17 data output; bit 1
D2 18 data output; bit 2
D3 19 data output; bit 3
D4 20 data output; bit 4
D5 21 data output; bit 5
D6 22 data output; bit 6
D7 23 data output; bit 7
D8 24 data output; bit 8
D9 25 data output; bit 9 (MSB)
IR 26 in range data output
DGND1 27 digital ground 1
VCCD1
28 digital supply voltage 1 (+5 V)
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CLK 1
28 VCCD1
TC 2
VCCA 3
27 DGND1
26 IR
AGND 4
25 D9
n.c. 5
24 D8
VRB 6
23 D7
VRM 7
22 D6
TDA8763A
VI 8
21 D5
VRT 9
20 D4
OE 10
VCCD2 11
DGND2 12
19 D3
18 D2
17 D1
V CCO 13
OGND 14
16 D0
15 n.c.
MBG914
Fig.2 Pin configuration.
1999 Jan 06
5
5 Page 
Philips Semiconductors
10-bit high-speed low-power ADC
Product specification
TDA8763A
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
a) The current flowing into the resistor ladder is IL = R-----O---V-B---R-+---T--R--–---L--V--+--R---R-B---O----T- and the full-scale input range at the converter,
to cover code 0 to code 1023, is VI = RL × IL = R-----O----B----+-----RR-----LL----+-----R----O----T- × (V RT + –VRB ) = 0˙.852 × (V RT – VRB )
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
R-----O-----B------+-----RR-----LL-----+----R-----O-----T-- will be kept reasonably constant from device to device. Consequently variation of the output
codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
4. EG = --(--V----1---0--2---3----–V----V-i--(--0p--)-–----p–---)-V-----i--(--p---–----p---) × 100
5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = ENOB × 6.02 + 1.76 dB.
8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
10. Output data acquisition: the output data is available after the maximum delay time of td(max). For 50 MHz version it is
recommended to have the lowest possible output load.
1999 Jan 06
handbook, halfpage
VRT
VRM
VRB
RLAD
ROT
RL
IL
code 1023
code 0
ROB
MGD281
Fig.3 Explanation of note 3.
11
11 Page | ||
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| PDF Descargar | [ Datasheet TDA8763A.PDF ] | |
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