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PDF TDA8761 Data sheet ( Hoja de datos )

Número de pieza TDA8761
Descripción 9-bit analog-to-digital converter for digital video
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! TDA8761 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
TDA8761
9-bit analog-to-digital converter for
digital video
Preliminary specification
File under Integrated Circuits, IC02
1995 Mar 20
Philips Semiconductors

1 page




TDA8761 pdf
Philips Semiconductors
9-bit analog-to-digital converter for
digital video
Preliminary specification
TDA8761
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
VCCD
VCCO
VCC
VI
Vi(p-p)
IO
Tstg
Tamb
Tj
PARAMETER
analog supply voltage
digital supply voltage
output stages supply voltage
supply voltage differences between
VCCA and VCCD
VCCO and VCCD
VCCA and VCCO
input voltage
AC input voltage for switching
(peak-to-peak value)
output current
storage temperature
operating ambient temperature
junction temperature
CONDITIONS
note 1
note 1
note 1
referenced to AGND
referenced to DGND
MIN.
0.3
0.3
0.3
MAX.
+7.0
+7.0
+7.0
UNIT
V
V
V
1.0
1.0
1.0
0.3
55
0
+1.0
+1.0
+1.0
+7.0
VCCD
10
+150
+70
+150
V
V
V
V
V
mA
°C
°C
°C
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided the difference
between VCCA, VCCD and VCCO is between 1 and +1 V.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
110
UNIT
K/W
1995 Mar 20
5

5 Page





TDA8761 arduino
Philips Semiconductors
9-bit analog-to-digital converter for
digital video
Preliminary specification
TDA8761
handbook, full pagewidth
V CCD
CE
50 %
output
data
output
data
t dLZ
t dZL
HIGH
HIGH
t dHZ
t dZH
90 %
LOW
50 %
LOW 10 %
TDA8761
CE
50 %
3.3 k
15 pF
V CCD
S1
TEST
t dLZ
t dZL
t dHZ
t dZH
S1
VCCD
VCCD
GND
GND
MGC358
fCE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
1995 Mar 20
11

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