PDF TDA8757 Data sheet ( Hoja de datos )

Número de pieza	TDA8757
Descripción	Triple 8-bit ADC 170 Msps
Fabricantes	NXP Semiconductors
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No Preview Available ! TDA8757 Triple 8-bit ADC 170 Msps Rev. 07 — 28 February 2002 Preliminary data 1. General description The TDA8757 is a triple 8-bit ADC for the digitizing of large bandwidth RGB/YUV signals at a sampling rate up to 170 Msps. The IC supports display resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The IC also includes a PLL that can be locked to the horizontal line frequency and generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics applications. An external clock signal can also be used to clock the ADC. The outputs are available either on one port up to 110 Msps or on two ports up to 170 Msps. The operating mode is selectable with the serial interface to for either I2C-bus or 3-wire serial bus (3W-bus) operation. The clamp level, the gain and the other settings are controllable through the serial interface. 2. Features s Triple 8-bit ADC s Sampling rate up to 170 Msps s IC controllable by a serial interface which can be I2C-bus or 3W-bus, selected by a TTL input pin s Three clamps for programming a clamping code from −63.5 to +64 in steps of 1⁄2 LSB (RGB) and from +120 to +136 in steps of 1⁄2 LSB (YUV) s Three controllable ampliﬁers: gain controlled by the serial interface to produce a full-scale resolution of 1⁄2 LSB peak-to-peak s Ampliﬁer bandwidth of 250 MHz s Low gain variation with temperature s PLL controllable through the serial interface to generate the ADC clock which can be locked to any line frequency of 15 to 150 kHz s Integrated PLL divider s Programmable phase clock adjustment cells s Internal voltage regulators s TTL compatible digital inputs and outputs s Outputs on one port or demultiplexed on two ports; selectable with the serial interface s Chip enable, high-impedance ADC output s Power-down mode s 1.5 W power dissipation s Sync on green extractor. 1 page Philips Semiconductors TDA8757 Triple 8-bit ADC 170 Msps CLP AGCα OE CLPα INα VREF VP 150 kΩ CLAMP CONTROL MUX AGC CKDMX DAC I2C-bus: CKADC 8 8 bits (Oα) REGISTER OUTPUTS A & OUTPUTS B ADC 8 8 A0α to A7α B0α to B7α ORα DAC 5 REGISTER FINE GAIN ADJUST I2C-bus: 5 bits (Fα) D8 DR R 8 17 1 REGISTER COARSE GAIN ADJUST HSYNC GAINCα Fig 2. Channel diagram (where α stands for R, G or B). I2C-bus: 3 bits (Dmx, Odda, Shift, Blk) I2C-bus: 7 bits (Cα) SERIAL I2C-BUS SDA SCL BOTα FCE695 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 5 of 37 5 Page Philips Semiconductors TDA8757 Triple 8-bit ADC 170 Msps Table 3: Pin description…continued Symbol Pin Description VCCO(PLL) n.c. 126 127 PLL output supply voltage not connected DGND1 128 digital ground 1 OE 129 output enable; active LOW (when OE is HIGH, the outputs are high-impedance) PD 130 power-down control input (IC is in Power-down mode when this pin is HIGH) CLP 131 clamp pulse input (clamp active HIGH) HSYNC 132 horizontal synchronization pulse input INV 133 PLL clock output inverter control input (invert when HIGH) CKEXT 134 external clock input COAST 135 PLL coast control input CKREF 136 PLL reference clock input VCCD1 n.c. 137 digital supply voltage 1 138 not connected AGNDPLL CP 139 140 PLL analog ground PLL ﬁlter input CZ 141 PLL ﬁlter input AGNDPLL VCCA(PLL) n.c. 142 143 144 PLL analog ground PLL analog supply voltage not connected GNDDP exposed die pad connection 8. Functional description This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals, coming from an analog source, into digital data used by a LCD driver (pixel clock up to 170 MHz). 8.1 Analog video inputs The RGB/YUV video inputs are externally AC coupled and are internally DC polarized. The synchronization signals are also used for the internal PLL and the gain calibration. If the green video signal has composite sync (sync on green), it is possible to extract this composite sync by connecting the green signal to pin INSOG (AC coupled). When the sync pulse amplitude is below 300 mV, the I2C-bus bit ‘Slevel’ has to be set to logic 1 (see Figure 5). The maximum amplitude for the sync pulse is 600 mV. The composite sync is available at pin SOGO (TTL level compatible signal). 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 11 of 37 11 Page

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