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Número de pieza	TDA8751T
Descripción	QPSK receiver
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA8051 QPSK receiver Product speciﬁcation Supersedes data of 1998 Jan 08 File under Integrated Circuits, IC02 1999 Aug 20 1 page Philips Semiconductors QPSK receiver Product speciﬁcation TDA8051 FUNCTIONAL DESCRIPTION The QPSK modulated signal is applied to the input as an asymmetrical RF signal in the bandwidth 44 to 130 MHz. The spectrum extension to this waveform must be limited by a band-pass filter superseding the IC. The RF input is either the LNA input, if the level is −30 to 0 dBmVrms, or the DEMOD input if the level is −20 to +10 dBmVrms. The amplified RF signal is then mixed with two clocks in quadrature to provide the base-band demodulated In-phase (I) and Quad-phase (Q) signals. The VCO operates at twice the RF carrier frequency in the bandwidth 88 - 260 MHz (one octave), therefore the 0 to 90° clocks are generated by a divider by 2. The VCO frequency can be programmed by an integrated PLL that tunes the external LC tank circuit. The raw I and Q generated signals contain spurious spikes, therefore each signal is passed through a third order active low-pass filter (RC cell + Sallen-Key structure), whose cut-off frequency is set by external components. The filtered I and Q data signals are then amplified to provide balanced buffer outputs. The data sent to the PLL is loaded in bursts, framed by signal EN. Programming clock edges, together with their relevant data bits, are ignored until EN becomes active (LOW). The internal latches are updated with the latest programming data when EN returns to inactive (HIGH). The last 14 bits only are retained within the programming register. No check is made on the number of clock pulses received while programming is enabled. An active clock edge causing a shift of the data bits is generated when EN goes HIGH while CLOCK is still LOW. The main divider ratio and the reference divider ratio are provided via the serial bus (see Table 1). LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC V(max) tsc Tstg Tj(max) Tamb VCC(tune) PARAMETER supply voltage maximum voltage on all pins except pin 9 (5 V) maximum short circuit duration on outputs storage temperature maximum junction temperature operating ambient temperature tuning voltage supply MIN. −0.3 −0.3 − −40 − 0 −0.3 MAX. 6.0 VCC 10 +150 150 70 30 UNIT V V s °C °C °C V HANDLING HBM ESD: The IC pins withstand 2 kV except pin 26 (1750 V). MM ESD: The IC pins withstand 100 V except pins 2 and 31 (75 V). THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth(j-a) thermal resistance from junction to ambient CONDITIONS in free air VALUE 65 UNIT K/W 1999 Aug 20 5 5 Page Philips Semiconductors QPSK receiver Product speciﬁcation TDA8051 handbook, full pagewidth 105 MHz DEMOD_IN +5 V 103 MHz maximum input level 10 dB above max. input level = 20 dBmVrms 103 105 f (MHz) × 0¡ 90¡ × I_OUT1 VCO 200 MHz Q_OUT1 + 22 dBmVrms AM_REJ baseband demodulated AM (15 KHz spacing) 3 f (MHz) AM sidebands (15 KHz offset) FCE173 Fig.4 AM rejection test. handbook, full pagewidth 1999 Aug 20 22 dBmV 300 kHz 22 dBmV 500 kHz I_OUT2 Q_OUT2 I_OUT I_OUTC Q_OUT Q_OUTC FCE174 Fig.5 IM3 measurement of the output section. 11 11 Page

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