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Número de pieza | TDA8586 | |
Descripción | Power amplifier with load detection and auto BTL/SE selection | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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No Preview Available ! INTEGRATED CIRCUITS
DATA SHEET
TDA8586
Power amplifier with load detection
and auto BTL/SE selection
Preliminary specification
Supersedes data of 1998 May 25
File under Integrated Circuits, IC01
1999 Apr 08
1 page Philips Semiconductors
Power amplifier with load detection and
auto BTL/SE selection
Preliminary specification
TDA8586
handbook, full pagewidth
2
IN1
1
n.c.
TDA8586TH
VP1
18
−
60
kΩ
V/I
+
+
60
kΩ
V/I
−
VP2
13
−
OA
+
17 OUT1
−
VPn OA
+
19 HVP1
3
IN2
4
IN3
6
ACREF
VPn
30 kΩ
5
IN4
BUFFER
+
60
kΩ
V/I
−
−
60
kΩ
V/I
+
+
60
kΩ
V/I
−
+
60
kΩ
V/I
−
+
OA
−
20 OUT2
−
OA
+
14 OUT3
−
VPn OA
+
+
OA
−
12 HVP2
11 OUT4
8
MSO
INTERFACE
10 9
DDDSEL OVERRULE
DIAGNOSTIC
7 DIAG
15
PGND2
16
PGND1
MGR024
1999 Apr 08
Fig.2 Block diagram SOT418-2 (HSOP20 heatsink up).
5
5 Page Philips Semiconductors
Power amplifier with load detection and
auto BTL/SE selection
Preliminary specification
TDA8586
CHARACTERISTICS
VP = 14.4 V; Tamb = 25 °C; fi = 1 kHz; RL = ∞; measured in test circuit of Fig.8; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
VP
Iq(tot)
Istb
VO
VP(mute)
Vo
operating supply voltage
total quiescent current
standby current
DC output voltage
low supply voltage mute
single-ended and bridge-tied
load output voltage
SE mode
VP = 14.4 V
VP = 14.4 V; RL = 4 Ω
mute condition
on condition
VI DC input voltage
VP = 14.4 V
PIN MSO
VMSO
voltage at pin MSO
standby condition
mute condition; note 1
on condition
IMSO
input current
mute pin at standby condition;
VMSO < 0.8 V
Diagnostic; output buffer (open-collector); see Figs 7 to 8
VDIAG(L)
ILI
VDIAG(or)
diagnostic output voltage LOW Isink = 1 mA
leakage current
VDIAG = 14.4 V
diagnostic override voltage in mute mode after load
detection
VDIAG(4ch) diagnostic 4 channel indication mute, after load detection with
voltage
4 speakers connected
CD2
CD10
clip detector LOW
clip detector HIGH
THD mode; VDIAG > 3 V;
R = 10 kΩ
THD mode (default);
VDIAG > 3 V; R = 10 kΩ
CLIP DETECT CONTROL PIN
VDDDSEL
voltage at DDD select pin to
obtain:
10% DDD
2% DDD
IDDDSEL
Input current DDD select pin VDDDSEL = 5 V
8.0
−
−
−
6.0
−
−
−
0
2.0
8.0
−
−
−
10.5
−
0.5
7
0
3
15
14.4
140
1
7.0
7.0
−
−
4.0
−
3.0
−
5
0.3
−
−
0.3
2
10
−
−
−
18
170
100
−
8.0
20
100
−
0.8
4
10.5
40
0.8
1
18
0.8
3.5
13
1
6
140
V
mA
µA
V
V
mV
mV
V
V
V
V
µA
V
µA
V
V
%
%
V
V
µA
1999 Apr 08
11
11 Page |
Páginas | Total 24 Páginas | |
PDF Descargar | [ Datasheet TDA8586.PDF ] |
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