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PDF TDA8443A Data sheet ( Hoja de datos )
| Número de pieza | TDA8443A | |
| Descripción | I2C-bus controlled YUV/RGB switch | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8443A
I2C-bus controlled YUV/RGB switch
Product specification
Supersedes data of November 1992
File under Integrated Circuits, IC02
1995 Mar 07
Philips Semiconductors
1 page  
Philips Semiconductors
I2C-bus controlled YUV/RGB switch
Product specification
TDA8443A
FUNCTIONAL DESCRIPTION
The circuit contains two sets of inputs (see Fig.1). Both
channels can receive RGB or YUV signals. Each set of
inputs has its own synchronization input, which internally
generates a pulse to clamp the inputs. The internal
clamping pulse can also be controlled by a signal (e.g. a
sandcastle pulse) applied to pin 24. The pulse will occur
during the time that the signal at pin 24 is between
5.5 and 6.5 V. If both a sync signal and a pin 24 signal are
used the signal should be applied to pin 24 via a 1 kΩ
resistor.
RGB signals of Channel 2 can be matrixed to YUV signals.
The outputs can be set in a high impedance OFF state,
which allows the use of seven devices in parallel
(I2C-bus mode).
The circuit can be controlled by an I2C-bus compatible
microcontroller or directly by DC voltages. The fast
switching input can be operated via pin 16 of the
peritelevision connector.
I2C-bus mode
The protocol for the devices in I2C-bus mode is shown
in Fig.3.
Table 1 Protocol bit description
BIT
STA
MA2 to MA0
ACK
D7
D6
D5 to D3
D2
D1 and D0
STO
DESCRIPTION
start condition
address selection bits; see Table 2
acknowledge bit
channel selection bit; see Table 3
matrix selection bit; see Table 3
gain control bits; see Table 4
fast switching priority bit; see Table 5
output state control bits; see Table 6
stop condition
handbook, full pagewidthSTA 1 1 0 1 MA2 MA1 MA0 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STO
MSA003
See Table 1.
Fig.3 I2C-bus protocol.
1995 Mar 07
5
5 Page 
Philips Semiconductors
I2C-bus controlled YUV/RGB switch
Product specification
TDA8443A
TIMING CHARACTERISTICS
I2C-bus load conditions: 4 kΩ pull-up resistor to +5 V; 200 pF capacitor to GND;
all values are referenced to VIH = 3 V and VIL = 1.5 V; see Fig.4.
SYMBOL
PARAMETER
CONDITIONS
MIN.
tBUF
tSU;STA
tHD;STA
tLOW
tHIGH
tr
tf
tSU;DAT
tHD;DAT
tSU;ACK
tHD;ACK
tSU;STO
time bus must be free before start
set-up time for start condition
hold time for start condition
SCL and SDA LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time (write)
data hold time (write)
acknowledge set-up time
acknowledge hold time
set-up time for stop condition
note 1
4.7
4.7
4.0
4.7
4.0
−
−
250
1.0
−
0
4.7
TYP.
−
−
−
−
−
1.0
0.3
−
−
2
−
−
MAX.
µs
µs
µs
µs
µs
µs
µs
ns
µs
µs
µs
µs
Note
1. Timing tHD;DAT deviates from the I2C-bus specification. After reset has been activated, a delay of 50 µs must occur
before transmission may be resumed.
handbook, full pagewidth SDA
(WRITE)
t BUF
SCL
t SU; STA
t HD; DAT
tf tr
t LOW
t HD; STA
t SU; ACK
t LOW
t HD; ACK
t HIGH
t SU; DAT
t SU; STO
MLD005
1995 Mar 07
Fig.4 I2C-bus timing diagram.
11
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| PDF Descargar | [ Datasheet TDA8443A.PDF ] | |
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