|
|
PDF TDA8433 Data sheet ( Hoja de datos )
| Número de pieza | TDA8433 | |
| Descripción | Deflection processor for computer controlled TV receivers | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TDA8433 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
INTEGRATED CIRCUITS
DATA SHEET
TDA8433
Deflection processor for computer
controlled TV receivers
Product specification
File under Integrated Circuits, IC02
August 1991
1 page  
Philips Semiconductors
Deflection processor for computer
controlled TV receivers
Product specification
TDA8433
PIN FUNCTIONS
Pin 1 - Ao subaddress
The Ao bit is the least significant bit
of the bus-address. It enables two
TDA8433s, with different
addresses, to be connected to the
same bus.
Pin 2 - Vertical sync input
Positive trigger pulses of > 3 V are
sufficient to exceed the internal
threshold of the ramp generator.
Flyback and blanking will then start
and, during the blanking period, the
circuit will be inhibited for further
input pulses (see Fig.3). It should be
noted that the TDA8433 has no
vertical oscillator therefore, the sync
processor, which is used in this
combination, has to provide trigger
pulses as well when the video input
is absent.
Pin 3 - Vertical blanking
The positive going blanking pulse is
fed from a current source. The
blanking period is fixed by the
capacitor connected to pin 5 and the
resistor connected to pin 4 (see
Fig.3).
Pins 4 and 5 - Reference/flyback
timing
The external resistor connected
between pin 4 and ground provides
a reference current for the triangle
generator circuit. This circuit
generates the triangle waveform at
pin 5. The width of the blanking
pulse is set by the external
capacitor connected to pin 5.
Table 1 Sync processor time constants
VTRA
'0'
'0'
'1'
'1'
VTRC OUTPUT
TIME CONSTANT
'0' 12 V
automatic operation
'1' 5.3 V medium
'0' 1.5 V fast (video recorder)
'1' 0.2 V not to be used
Pin 6 - DACC (tau switching)
The output voltage, which depends
on the VTRA and VTRC bits in the
I2C-bus control register, is connected
to the coincidence detector of the
sync processor. In this way the time
constants of the horizontal PLL (in the
sync processor) can be set. If the
TDA2579 is used (see Fig.6) the
effect will be as listed in Table 1.
Pin 7 - DACB (horizontal phase)
The voltage at pin 7 is fed to the
horizontal pulse modulator in the sync
processor. This voltage, together with
the signal produced by the phase 2
detector during horizontal flyback,
sets the phase of the horizontal
output with respect to the flyback
pulse in the horizontal output stage.
The voltage range is variable
between 0.05 V and 10 V.
Pin 8 - DACA (horizontal
frequency)
The frequency of the horizontal
oscillator in the external sync
processor is adjusted by the voltage
level at pin 8. The voltage is variable
in 63 steps from 0.05 V to 10 V (i.e.
0.158 V per step).
Pin 9 - OUT (video switch)
The output at pin 9 is controlled by the
CVBS bit from the control register
where
CVBS = logic 0; the output is HIGH
(open collector)
CVBS = logic 1; the output is LOW
(saturation voltage)
An external video selector can be
controlled by means of this switching
function.
Pins 10 and 17 - I/O and Voltage
reference
Pin 10 is connected to the output of
the phase 1 detector in the sync
processor. Whether the pin is used as
an input or an output is dependent on
the PHI1 bit of the horizontal
frequency (HFREQ) register. When
PHI = logic 0 (output transistor open)
pin 10 is used as an input. The DC
information at this pin is compared
with the reference voltage at pin 17
and is reflected in the HCENT of the
status register.
HCENT = logic 0; input > Vref at V17
HCENT = logic 1; input < Vref at V17
In this way the free running frequency
can be adjusted by computer while
the oscillator is locked. Alternatively,
when PHI1 = logic 1, pin 10 is
switched to ground. The free running
frequency of the oscillator can the be
adjusted while watching the screen
provided that pin 10 is connected to
the video input of the sync processor.
Pin 11 -IN (HLOCKN and 50/60 Hz)
This pin is connected to the combined
MUTE and 50/60 Hz pin of the sync
processor. The various DC levels
define the state of the HLOCKN and
50/60 Hz bits in the status register
(see Table 2.)
August 1991
5
5 Page 
Philips Semiconductors
Deflection processor for computer
controlled TV receivers
Product specification
TDA8433
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
IN HLOCKN and 50/60 Hz (pin 11)
V11 HLOCKN switching level
V11 switching level where:
LOCKN = '0'
LOCKN = '1'
V11 switching level where:
50/60 Hz = '0'
50/60 Hz = '1'
I11 source current
state 50 Hz
− 0.7
1.0 −
−−
−
0.8 VCC
10
−
−
25
−V
−V
0.4 V
0.7 VCC
−
35
V
V
µA
SDA serial data input (pin 14)
V14 switching level where:
SDA = ‘0’
SDA = ‘1’
I14 sink current
−−
3.0 −
− 0.5
1.5 V
−V
10 µA
SCL serial clock input (pin 15)
V15 switching level where:
SDA = ‘0’
SDA = ‘1’
I15 sink current
−−
3.0 −
− 0.5
1.5 V
−V
10 µA
Internal supply voltage
V16 maximum allowed load
1 mA load
V17 voltage reference for pin 10 (pin 17)
I17 input load current
4.5 5.0
1.0 −
−−
5.5 V
Vcc − 1.5 V
2.0 µA
E-W drive output (pin 19; see application information)
V19 output voltage
I19 output current
RR ripple rejection
RI internal resistance
tR response time
1 mA load
0.5 −
±1.0 −
24 30
−1
−2
11.5 V
±2.0 mA
− dB
2 kΩ
− µs
Vertical drive output (pin 20; see application information)
V20 output voltage
I20 output current
RR ripple rejection
DAC stepsize
1 mA load
note 2
note 3
0.5 −
±1.5 ±2.0
35 40
10 −
10.5 V
− mA
− dB
190 %
Vertical feedback (pin 21; see application information: Register 02 = 20H, 03 = 0, 04 = 0, 05 = 20H, 06 = 0)
V21
V21(p-p)
I21
DC input voltage
AC output voltage (peak-to-peak
value)
input current
note 2
1.7 1.85
1.65 1.8
−−
2.05 V
1.95 V
−3 µA
August 1991
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet TDA8433.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TDA8432 | Computer-Controlled Deflection Processor for Video Displays |  Signetics |
| TDA8433 | Deflection processor for computer controlled TV receivers | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |