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PDF TDA8425 Data sheet ( Hoja de datos )
| Número de pieza | TDA8425 | |
| Descripción | Hi-fi stereo audio processor; I2C-bus | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8425
Hi-fi stereo audio processor;
I2C-bus
Product specification
File under Integrated Circuits, IC02
October 1988
1 page  
Philips Semiconductors
Hi-fi stereo audio processor; I2C-bus
Product specification
TDA8425
Bass control
The bass control stage can be switched from an emphasis of 15 dB to an attenuation of 12 dB for low frequencies in
steps of 3 dB.
Treble control
The treble control stage can be switched from +12 dB to −12 dB in steps of 3 dB.
Bias and power supply
The TDA8425 includes a bias and power supply stage, which generates a voltage of 0.5 × VCC with a low output
impedance and injector currents for the logic part.
Power-on reset
The on-chip power-on reset circuit sets the mute bit to active, which mutes both parts of the treble amplifier. The muting
can be switched by transmission of the mute bit.
I2C-bus receiver and data handling
Bus specification
The TDA8425 is controlled via the 2-wire I2C-bus by a microcomputer.
The two wires (SDA − serial data, SCL − serial clock) carry information between the devices connected to the bus. Both
SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor.
When the bus is free both lines are HIGH.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW. The set up and hold times are specified in AC
CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as a start condition.
A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as a stop condition.
The bus receiver will be reset by the reception of a start condition. The bus is considered to be busy after the start
condition.
The bus is considered to be free again after a stop condition.
Module address
Data transmission to the TDA8425 starts with the module address MAD.
October 1988
Fig.3 TDA8425 module address.
5
5 Page 
Philips Semiconductors
Hi-fi stereo audio processor; I2C-bus
Product specification
TDA8425
AC CHARACTERISTICS (1)
VCC = 12 V; bass/treble in linear position; pseudo and spatial stereo off; RL > 10 kΩ; CL < 1000 pF;
Tamb = 25 °C; unless otherwise specified
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
I2C bus timing (see Fig.7)
SDA, SCL (pin 11 and 12)
Clock frequency range
The HIGH period of the clock
The LOW period of the clock
SCL rise time
SCL fall time
Set-up time for start condition
Hold time for start condition
Set-up time for stop condition
Time bus must be free before
a new transmission can start
Set-up time DATA
INPUTS
fSCL
tHIGH
tLOW
tr
tf
tSU; STA
tHD; STA
tSU; STO
tBUF
tSU; DAT
0−
4−
4.7 −
−−
−−
4.7 −
4−
4.7 −
4.7 −
250 −
100
−
−
1
0.3
−
−
−
−
−
IN1 L (pin 18) IN1 R (pin 20);
IN2 L (pin 1) IN2 R (pin 3)
Input signal handling (RMS value)
at Vu = −12 dB; THD ≤ 0.5%
Input resistance
Frequency response (−0,5 dB)
bass and treble in linear position;
stereo mode; effects off
Vi(rms)
Ri
f
2 −−
20 30 40
20 −
20 000
OUTPUTS
OUT R (pin 9); OUT L (pin 13)
Output voltage range (rms value)
at THD ≤ 0.7%; Vi(max) ≤ 2 V
Load resistance
Output impedance
Signal plus noise-to-noise ratio (weighted
according to CCIR 468-2); VO = 600 mV
gain = 6 dB
gain = 0 dB
gain = ≤ −20 dB
Crosstalk between inputs at gain = 0 dB;
1 kHz; opposite inputs grounded (50 Ω);
IN1L (pin 18) to IN2L (pin1) or
IN1R (pin 20) to IN2R (pin 3)
Vo(rms)
RL
ZO
(S+N)/N
(S+N)/N
(S+N)/N
0.6 −
10 −
−−
−
−
100
− 78 −
− 86 −
− 68 −
αcr − 100 −
UNIT
kHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
V
kΩ
Hz
V
kΩ
Ω
dB
dB
dB
dB
October 1988
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet TDA8425.PDF ] | |
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