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PDF TDA8415 Data sheet ( Hoja de datos )
| Número de pieza | TDA8415 | |
| Descripción | TV and VTR stereo/dual sound processor with integrated filters and I2C-bus control | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8415
TV and VTR stereo/dual sound
processor with integrated filters and
I2C-bus control
Preliminary specification
File under Integrated Circuits, IC02
May 1989
1 page  
Philips Semiconductors
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
Preliminary specification
TDA8415
PINNING
1
2
3
4
5
6
7
8
9
10
Control port C1
SDA, serial data line (I2C-bus)
SCL, serial clock line (I2C-bus)
Oscillator input (or quartz)
Digital ground (0 V)
Not connected, but reserved
Sound channel input AF2 (E2)
Sound channel input AF1 (E1)
External AF input (E4)
External AF input (E3)
11 Output A4 AF 2 output
12 Output A3 AF 2 output
13 Output A2 AF 1 output
13 Output A1 AF 1 output
15 Supply voltage VP
16 Analogue ground (0 V)
17 Ripple rejection improvement
18 Mute input
19 Control port C2
20 Not connected, but reserved
FUNCTIONAL DESCRIPTION
Anti-aliasing filters
Frequency band limitation is performed by a second order Sallen and Key low-pass filter inserted in the AF signal path
and the identification circuit. This limitation is necessary because of the time-discrete signal processing needed to meet
the Nyquist criterion.
Identification
To enable the identification of the transmitted AF signal (mono, stereo or dual sound), the carrier frequency of the second
channel (E2) is also modulated by an identification signal. The identification signal is a 54.6875 kHz pilot carrier signal
which is 50% amplitude modulated by either a 117.4 Hz signal for stereo transmission or by a 274.1 Hz signal for dual
sound transmission.
The identification section of the circuit consists of a 54 kHz high-pass filter followed by a gain controlled amplifier with an
AM demodulator. The total gain of the high-pass filter and the amplifier is approximately 56 dB. The demodulated
identification signal is filtered by the identification band-pass filters, (117.4 Hz for stereo transmission, 274.1 Hz for dual
sound transmission). The output from either filter is converted to a DC signal by a peak detector and the necessary
hysteresis is performed by a Schmitt-trigger. The resultant DC output signals indicate the status of the transmitter (mono,
stereo or dual sound).
De-matrix and de-emphasis
Depending on the results of the identification circuit (mono, stereo or dual sound) the AF signals at the inputs E1 and E2
are converted to the signals at E1* and E2* as listed in Table 1.
Table 1 Transmitter status
TRANSMITTER STATUS (1)
mono
stereo
dual sound
E1
0.7(L+R)
0.7(L+R)
0.7A
E2
−
2R
B
E1*
2(L+R)
4L
2A
E2*
−
4R
2B
Note
1. Where L = left channel signal; R = right channel signal; A = first sound channel signal and B = second sound channel
signal.
This section of the circuit also performs the de-emphasis (50 µs time constant) with a high degree of accuracy.
May 1989
5
5 Page 
Philips Semiconductors
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
Preliminary specification
TDA8415
Table 5 defines the contents of the switch register.
Table 5 Switch register
SWITCH
REGISTER
sound mute −
INPUT
OUTPUT
D7 D6 D5 D4 D3 D2 D1 D0 (HEX)
E1 E2 E3 E4 A1 A2 A3 A4
− − − − no signal
0 0 0 0 0 0 0 0 (00)
mono
M M M − − M M M M 0 0 0 1 0 0 0 0 (10)
St L* R − − L* L* L* L* 0 0 0 1 0 0 0 0 (10)
stereo
St L* R − − L R L R 0 0 1 0 1 0 1 0 (2A)
sound A DS A B − − A A A A 0 0 0 1 0 0 0 0 (10)
sound B DS A B − − B B B B 0 0 0 1 1 1 1 1 (1F)
dual sound DS A B − − A A B B 0 0 0 1 1 1 0 0 (1C)
DS A B − − B B A A 0 0 0 1 0 0 1 1 (13)
dual sound DS A B − − A B A A 0 0 0 1 0 0 1 0 (12)
mix DS A B − − A A A B 0 0 0 1 1 0 0 0 (18)
DS A B − − A B A B 0 0 0 1 1 0 1 0 (1A)
DS A B − − B B A B 0 0 0 1 1 0 1 1 (1B)
DS A B − − A B B B 0 0 0 1 1 1 1 0 (1E)
external
− − − E3 E4 E3 E3 E3 E3 0 1 1 1 0 0 0 0 (70)
− − − E3 E4 E4 E4 E4 E4 0 1 1 1 1 1 1 1 (7F)
− − − E3 E4 E3 E4 E3 E4 0 1 1 1 1 0 1 0 (7A)
− − − E3 E4 E4 E4 E3 E3 0 1 1 1 0 0 1 1 (73)
− − − E3 E4 E3 E3 E4 E4 0 1 1 1 1 1 0 0 (7C)
− − − E3 E4 E3 E4 E3 E3 0 1 1 1 0 0 1 0 (72)
− − − E3 E4 E3 E3 E3 E4 0 1 1 1 1 0 0 0 (78)
− − − E3 E4 E4 E4 E3 E4 0 1 1 1 1 0 1 1 (7B)
− − − E3 E4 E3 E4 E4 E4 0 1 1 1 1 1 1 0 (7E)
Note
1. Where: M = mono; St = stereo. DS = dual sound; R = right; L = left; L * = (L+R)/2; A = sound A; B = sound B.
May 1989
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet TDA8415.PDF ] | |
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