PDF TDA8060TS Data sheet ( Hoja de datos )

Número de pieza	TDA8060TS
Descripción	Satellite ZERO-IF QPSK down-converter
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA8060TS Satellite ZERO-IF QPSK down-converter Product speciﬁcation Supersedes data of 1998 May 29 File under Integrated Circuits, IC02 1999 Aug 30 1 page Philips Semiconductors Satellite ZERO-IF QPSK down-converter Product speciﬁcation TDA8060TS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vi(max) tsc(max) Tamb Tstg Tj PARAMETER supply voltage maximum input voltage on all pins maximum short-circuit time operating ambient temperature storage temperature junction temperature MIN. −0.3 −0.3 − −20 −55 − MAX. +6.0 VCC 10 +85 +150 150 UNIT V V s °C °C °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth(j-a) thermal resistance from junction to ambient CONDITIONS in free air VALUE 120 UNIT K/W DC CHARACTERISTICS Tamb = 25 °C; VCC = 5 V; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS VCC supply voltage ICC supply current PEN = 5 V PEN = 0 V Conversion stage VI(RFA) DC input voltage on pin RFA VI(RFB) DC input voltage on pin RFB VO(IOUT) DC output voltage on pin IOUT VO(QOUT) DC output voltage on pin QOUT Quadrature generator VO(LOOUT) DC output voltage on pin LOOUT VO(LOOUTC) DC output voltage on pin LOOUTC Baseband stage VI(IBBIN) VI(QBBIN) VO(IBBOUT) VO(QBBOUT) DC input voltage on pin IBBIN DC input voltage on pin QBBIN DC output voltage on pin IBBOUT DC output voltage on pin QBBOUT MIN. 4.75 63 60 TYP. 5.00 73 70 MAX. 5.25 83 80 UNIT V mA mA − 0.9 − V − 0.9 − V − 2.0 − V − 2.0 − V − 4.7 − V − 4.7 − V − 2.5 − V − 2.5 − V − 2.5 − V − 2.5 − V 1999 Aug 30 5 5 Page This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 pF RF (2) RF 1 pF RFA 8 RFB 7 gain(1) COMGAIN 4 100 nF VCC(RF) RFGND VCC(LO1) LOGND1 VCC(LO2) LOGND2 6 9 16 15 19 22 LOW-PASS FILTER(3) 100 nF IOUT IBBIN 2 24 CONVERSION STAGE × 100 MHz I CONVERTER SYM ASYM LNA Q CONVERTER × 100 MHz SYM ASYM AMP 23 IBBOUT LOW-PASS FILTER(3) BASEBAND STAGE AMP 14 QBBOUT LOW-PASS FILTER(3) 0 to 5 V QUADRATURE GENERATOR PEN 5 DIVIDE-BY-2 STABILIZED LO PLL AND AMPLIFIER OSCILLATOR TDA8060TS 20 21 LOOUT LOOUTC 18 TKA 6Ω 1 pF 17 TKB 6Ω to PLL synthesizer IC BB835 20 (2×) kΩ 20 kΩ 11 13 QOUT QBBIN 100 nF LOW-PASS FILTER(3) Vtune from PLL synthesizer IC (1) Gain control voltage; minimum gain at 0.1 x VCC, maximum gain at 0.9 x VCC; 30 dB range. (2) Differential RF input 950 to 2200 MHz; level = −22 to −52 dBm per channel. (3) The filter input impedance is 400 Ω minimum. Fig.5 Application diagram. 1 VCC(BB1) 12 VCC(BB2) 3 BBGND1 10 BBGND2 MGM320 to I channel ADC to Q channel ADC 11 Page

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