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PDF TDA8020HL Data sheet ( Hoja de datos )
| Número de pieza | TDA8020HL | |
| Descripción | Dual smart card interface | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8020HL
Dual smart card interface
Product specification
Supersedes data of 2001 May 29
File under Integrated Circuits, IC02
2001 Aug 15
1 page  
Philips Semiconductors
Dual smart card interface
Product specification
TDA8020HL
PINNING
SYMBOL
PRES1
CGND1
CLK1
VCC1
RST1
I/O2
PRES2
CGND2
CLK2
VCC2
RST2
GND
VUP
SAP
SBP
VDDA
SBM
AGND
SAM
VDD
SCL
SDA
SAD0
SAD1
IRQ
CLKIN1
I/O1uC
I/O2uC
CLKIN2
CDEL
VDDI
I/O1
PIN DESCRIPTION
1 card 1 presence contact input (active HIGH)
2 ground connection output to card 1 (C5 contact)
3 clock output to card 1 (C3 contact)
4 supply voltage output to card 1 (C1 contact); decouple to pin CGND1 with 2 × 100 nF
capacitors with ESR < 100 mΩ
5 reset output to card 1 (C2 contact)
6 I/O contact to card 2 (C7 contact); internal 15 kΩ pull-up resistance to pin VCC2
7 card 2 presence contact input (active HIGH)
8 ground connection output to card 2 (C5 contact)
9 clock output to card 2 (C3 contact)
10 supply voltage output to card 2 (C1 contact); decouple to pin CGND2 with 2 × 100 nF
capacitors with ESR < 100 mΩ
11 reset output to card 2 (C2 contact)
12 ground connection
13 output of DC/DC converter; a 220 nF capacitor with ESR < 100 mΩ must be connected
to pin AGND
14 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SAP and SAM
15 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SBP and SBM
16 analog supply voltage for the DC/DC converter
17 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SBP and SBM
18 analog ground connection for the DC/DC converter
19 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SAP and SAM
20 power supply voltage
21 serial clock input of the I2C-bus (open drain)
22 serial data input/output of the I2C-bus (open drain)
23 I2C-bus address selection input 0
24 I2C-bus address selection input 1
25 interrupt request output to host (open drain; active LOW)
26 external clock input for card 1
27 I/O connection to host for card 1; internal 22 kΩ pull-up resistor to VDDI
28 I/O connection to host for card 2; internal 22 kΩ pull-up resistor to VDDI
29 external clock input for card 2
30 delay capacitor connection for the voltage supervisor (1 ms per 2 nF)
31 interface signals reference supply voltage
32 I/O contact to card 1 (C7 contact); internal 15 kΩ pull-up resistor to VCC1
2001 Aug 15
5
5 Page 
Philips Semiconductors
Dual smart card interface
Product specification
TDA8020HL
Deactivation sequence
When the session is completed, the microcontroller resets
bit START/STOP to logic 0 (t10). The circuit then executes
an automatic deactivation sequence (see Fig.5):
• Card reset (RST falls LOW) (t11)
• CLK is stopped (t12)
• I/O falls to 0 V (t13)
• VCC falls to 0 V with typical 0.14 V/µs slew rate (t14)
• The DC/DC converter is stopped (if both cards are
inactive) and CLK, RST, VCC and I/O become low
impedance to CGND (t15).
t11 = t10 + T/64; t12 = t11 + T/2; t13 = t11 + T;
t14 = t11 + 3T/2; t15 = t11 + 7T/2.
The deactivation time tde is the time that VCC needs to drop
below 0.4 V from START/STOP to logic 0 (t10).
handbook, full pagewidth
START/ STOP
RST
CLK
I/O
VCC
VUP
t10 t11
t de
t12 t13
t14
t15
Fig.5 Deactivation sequence.
FCE836
2001 Aug 15
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet TDA8020HL.PDF ] | |
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