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PDF TDA7580 Data sheet ( Hoja de datos )
| Número de pieza | TDA7580 | |
| Descripción | FM/AM DIGITAL IF SAMPLING PROCESSOR | |
| Fabricantes | ST Microelectronics | |
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TDA7580
FM/AM DIGITAL IF SAMPLING PROCESSOR
PRODUCT PREVIEW
s FM/AM IF SAMPLING DSP
s ON-CHIP ANALOGUE TO DIGITAL
CONVERTER FOR 10.7MHz IF SIGNAL
CONVERSION
s SOFTWARE BASED CHANNEL EQUALIZATION
s FM ADJACENT CHANNEL SUPPRESSION
s RECEPTION ENHANCEMENT IN MULTIPATH
CONDITION
s STEREO DECODER AND WEAK SIGNAL
PROCESSING
s 2 CHANNELS SERIAL AUDIO INTERFACE
(SAI) WITH SAMPLE RATE CONVERTER
s I2C AND BUFFER-SPI CONTROL INTERFACES
s RDS FILTER, DEMODULATOR & DECODER
s INTER PROCESSOR TRANSPORT
INTERFACE FOR ANTENNA AND TUNER
DIVERSITY
s FRONT-END AGC FEEDBACK
TQFP64
ORDERING NUMBER: TDA7580
DESCRIPTION
The TDA7580 is an integrated circuit implementing
an advanced mixed analogue and digital solution to
perform the signal processing of a AM/FM channel.
The HW&SW architecture has been devised so to
have a digital equalization of the FM/AM channel;
hence a real rejection of adjacent channels and any
other signals interfering with the listening of the de-
sired station. In severe Multiple Paths conditions, the
reception is improved to get the audio with high qual-
ity.
BLOCK DIAGRAM
A/D
HS3I
DAC
CGU
Oscillator
RDS
I2C/SPI
IF Digital
Signal Processor
I2C/SPI
SAI1
SAI0
SRC
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/31
1 page  
PIN DESCRIPTION
N° Name
1 VHI
2 VCM
3 VLO
4 INP
5 INN
6 VCMOP
7 GNDSD
8 GNDOSC
9 XTI
10 XTO
11 VDDOSC
12 VDDMTR
13 CKREFP
14 CKREFN
15 AGCKEY
16 GNDMTR
TDA7580
Type
Description
Notes
After
Reset
A Internally generated IFADC Opamps
It needs external 22µF
2.65V (@VDD=3.3V) Reference Voltage and 220nF ceramic
Pin for external filtering
capacitors
A Internally generated Common Mode
It needs external 22µF
1.65V (@VDD=3.3V) Reference Voltage and 220nF ceramic
Pin for external filtering
capacitors
A Internally generated IFADC Opamps
It needs external 22µF
0.65V (@VDD=3.3V) Reference Voltage and 220nF ceramic
Pin for external filtering
capacitors
A Positive IF signal input from Tuner
2.0Vpp @VDD=3.3V
A Negative IF signal input from Tuner
2.0Vpp @VDD=3.3V
A Internally generated Modulator Opamps It needs external 22µF
Common Mode 2.65V (@VDD=3.3V) and 220nF ceramic
Reference Voltage Pin for external
capacitors
filtering
G IFADC Modulator Analogue Ground
Clean Ground, to be
star-connected to
voltage regulator ground
G Oscillator Ground
Clean Ground, to be
star-connected to
voltage regulator ground
I High impedance oscillator input (quartz Maximum voltage swing
connection) or clock input when in
is VDD
Antenna Diversity slave mode
O Low impedance oscillator output (quartz
connection)
P Oscillator Power Supply
3.3V
P Tuner reference clock and AGCKeying 1.8V
DAC Power Supply
B Tuner reference clock positive output.
FM 100kHz
AMEU 18kHz
With internal pull_up, on
at reset
Output
B Tuner reference clock negative output. FM 100kHz
Output
AMEU 18kHz
With internal pull_up, on
at reset
A DAC output for Tuner AGCKeying
1.5kohm ±30% output
impedance. 1Vpp ±1%
output dynamic range
G Tuner reference clock and AGC keying
DAC Ground
5/31
5 Page 
TDA7580
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max. Unit
IozFT
5V Tolerant Tri-state Output
leakage (without pull up/down
device)
Vo = 0V or Vdd (note 1)
Vo = 5.5V
1 µA
1 3 µA
Ilatchup I/O latch-up current
V < 0V, V > Vdd
200
mA
Vesd Electrostatic Protection
Leakage, 1µA
2000
V
Note:
1. The leakage currents are generally very small, <1nA. The value given here, 1µA, is the maximum that can occur after an Electro-
static Stress on the pin.
2. On pins:17 to 20,23 to 26,29 to 33,36 to 39,42 to 46,49 to 52,55 to 58.
3. On pins: 13 and 14.
4. Same check on the analogue pin 15 (phisically without pull-up-down)
5. On pins:25, 26,32,49,50,55,56
6. On pins:17 to 20,23 to 24,29 to 31,33,36 to 39,42 to 46,51, 52,57, 58
LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max. Unit
Vil Low Level Input Voltage
1.70V<=VDD<=1.90V
0.3*VDD3 V
Vih High Level Input Voltage
1.70V<=VDD<=1.90V
0.8*VDD3
V
Vol Low level output Voltage
Iol = 4mA (notes 1)
0.15 V
Voh High level output Voltage
Iol = -4mA (notes 1)
VDD-0,15
V
Note: 1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability.
HIGH VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max. Unit
Vil Low Level Input Voltage
3.15V<=VDD3<=3.45V
0.8 V
Vih High Level Input Voltage
3.15V<=VDD3<=3.45V
2.0
V
Vol Low level output Voltage
Iol = XmA (notes 1 and 2)
0.15 V
Voh High level output Voltage
Iol = -XmA (notes 1 and 2)
VDD3-0.15
V
Note: 1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability
2. X=4mA for pins 17 to 20,29,30,32,36 to 39,42 to 46; X=8mA for pins 23 to 26,49 to 52,55 to 58.
CURRENT CONSUMPTION
Symbol
Parameter
IDD Current through VDD Power
Supply
IDDH
Current through VDDH Power
Supply
ISD Current through VSD Power
Supply
IOSCdc Current through VOSC Power
Supply
Test Condition
VDD=1.8V,VDD3=3.3V
All digital blocks working
VDD=1.8V,VDD3=3.3V
All I/Os working with 5pF load
VDD=1.8V,VDD3=3.3V
VDD=1.8V,VDD3=3.3V
without quartz
Min.
Typ.
120
Max.
200
Unit
mA
3 5 mA
36 45 54 mA
5.5 8 10.5 mA
11/31
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| PDF Descargar | [ Datasheet TDA7580.PDF ] | |
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