PDF TDA7535 Data sheet ( Hoja de datos )

Número de pieza	TDA7535
Descripción	DELTA/SIGMA CASCADE 20 BIT STEREO DAC
Fabricantes	ST Microelectronics
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No Preview Available ! TDA7535 DELTA/SIGMA CASCADE 20 BIT STEREO DAC s 20-bit resolution single ended output s Analog reconstruction third order Chebyshev filter s I2S input data format s On chip PLL s System clock: 64 Fs s 2 output channels s 0.9 VRMS single ended output dynamic s 3.3V power supply s Reset s Sampling rate 36KHz to 48KHz DESCRIPTION The TDA7535 is a stereo, digital-to-analog converter designed for audio application, including digital inter- polation filter, a third order multibit Delta-Sigma DAC, a third order Chebyshev's reconstruction filter and a differential to single ended output converter. This de- vice is fabricated in highly advanced CMOS, where high speed precision analog circuits are combined with high density logic circuits. The TDA7535, ac- cording to standard audio converters, can accept any I2S data format. BLOCK DIAGRAM TSSOP-14 SO-14 ORDERING NUMBER: TDA7535 The TDA7535 is available in SO-14 and TSSOP-14 packages. The total power consumption is less than 75mW. TDA7535 is suitable for a wide variety of applications where high performance are required. Its low cost and single 3.3V power supply make it ideal for sever- al applications, such as CD players, MPEG audio, MIDI applications, CD-ROM drives, CD-Interactive, digital radio applications and so on. An evaluation board is available to perform measurement and to make listening tests. DIGITAL I2S I2S INPUT 20 FS CLKOUT PLL FIR1 FIR2 FIR3 ALU 20 8FS S&H 23 64FS Σ∆ MODULATOR 4 D02AU1417 THERMO DECODER & RANDOMIZER 3rd CHEBYSHEV SC FILTER DIFF TO SINGLE CONVERTER ANALOG OUTPUT July 2003 1/9 1 page Figure 2. I2S Timings SDATA FSYNC SCK Valid tsckr Valid tsckf tlrw- tlrw+ tsds tsckpl tsdh tsckph tsck TDA7535 Timing Description Minimum tsck Clock Cycle(1) 1/(64Fs) - 150psRMS tsckpl SCK Phase Low 0.5tsck - 1% tsckph SCK Phase High 0.5tsck - 1% tlrw- FSYNC switching time window before SCK falling edge(2) 0 tlrw+ FSYNC switching time window after SCK falling edge(2) 0 tsds SDATA setup time 60 tsdh SDATA hold time 30 tsckr SCK rise time tsckf SCK fall time (1) (2) SCK clock defines the Fs, being FSYNC switches inside the time the Sample Rate. This input clock needs window as specified w.r.t. to falling edge a jitter below of SCK ~212psRMS Figure 3. Power Up & Reset Sequence Maximum 1/(64Fs) + 150psRMS 0.5tsck +1% 0.5tsck +1% 0.125tsck-10 0.125tsck-10 1.5 1.5 Unit ns ns ns ns ns ns ns ns ns VDD RESET TRES TRES Min 50ms I2S bit clock (SCK) must be present 20ms before reset release to allow PLL locking. D02AU1418 5/9 5 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
TDA7535	DELTA/SIGMA CASCADE 20 BIT STEREO DAC	ST Microelectronics

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