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PDF TDA7521 Data sheet ( Hoja de datos )

Número de pieza TDA7521
Descripción Analog Front End
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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TDA7521
Analog Front End
PRODUCT PREVIEW
TDA7521 is a BiCMOS analog front end for CD appli-
cations. Four input signals (AC*, BD*, E* and F*),
coming from the pick-up (whose laser diode is driven
and controlled by the device itself), are preamplified
by a programmable voltage-to-voltage or current-to-
voltage stage, depending on the used pick-up. The
output signals from the preamplifier stage (AC, BD, E,
F and HF, a radio frequency signal obtained by com-
bining the photo-detector outputs as A+B+C+D) are
fed to an 8-bit HF ADC (for HF, which carries encoded
audio data) and a 6-bit Servo ADC (for AC, BD, E and
F, used for focusing, tracking the laser beam and con-
trolling revolution speed). All these signals are digi-
tized, multiplexed, synchronized with the external
clock (768×Fs or 394×Fs, Fs=44.1KHz) and fed to the
digital counterpart in one only digital stream (AC/HF/
BD/HF/E/HF/F/HF). Two stereo DACs convert the in-
put bitstreams from TDA7522.
TQFP44
(10 x 10 x 1.40 mm body)
All the clock signals (for ADCs and DACs) are generated by a low-jitter PLL-based clock manager. All
TDA7521’s analog preprocessing is controlled by TDA7522 by means of an UART interface (which imple-
ments an I2C-like protocol). Housed in a TQFP 44, 10×10mm package, TDA7521 features the functions
shown in figure below.
TDA7521 uses the HF4CMOS technology and is supplied @5Vdc.
May 1998
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TDA7521 pdf
Figure 2. TDA7521 timings in 768×Fs mode
TDA7521
(1
(2
(3.A)
(3.B)
(3.C)
(3.D)
AC BD
E
F AC BD E
F (4
BD E
F AC BD E
F
(5
RF RF RF RF RF RF RF RF (6
RF RF RF RF RF RF RF RF (7
RBR
ER
FR A R B R
ER
FR
(8
A R B R E R F R A R B R E R F R (9
(10)
(11)
(12.A)
(12.B)
(12.C)
Fig.3.
A349 timing: (1) External clock ( 768 × FS mode); (2) Servo clock (servo data change on its
rising edge, while RF data change on the falling edge); (3.A, 3.B, 3.C, 3.D) Internally generated
96 × FS clocks for Servo ADC; (4) Servo data IN; (5) Servo data OUT; (6) RF data IN; (7) RF
data OUT; (8) AC/RF/BD/RF/E/RF/F/RF data stream before digital MUX; (9) Output
AC/RF/BD/RF/E/RF/F/RF; (10) Synthesized clock; (11) Generic Bitstream Input; (12.A, 12.B,
12.C) Possible synthesized 256 × FS (depending on the initial conditions)
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TDA7521 arduino
TDA7521
.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express writt en approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
® 1998 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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