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PDF TDA7500 Data sheet ( Hoja de datos )
| Número de pieza | TDA7500 | |
| Descripción | DIGITAL AM/FM SIGNAL PROCESSOR | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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® TDA7500
DIGITAL AM/FM SIGNAL PROCESSOR
PRODUCT PREVIEW
FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES
AM/FM PROCESSING
AUDIO-PROCESSING AND SOUND-PROC-
ESSING
HARDWARE RDS FILTER, DEMODULATOR
& DECODER
INTEGRATED CODEC
IIC AND SPI CONTROL INTERFACES
SPI DEDICATED TO DISPLAY MICRO
6 CHANNEL SERIAL AUDIO INTERFACE SAI
SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER
EXTERNAL MEMORY INTERFACE
DOUBLE DEBUG INTERFACE
ON-CHIP PLL
5V-TOLERANT 3V I/O INTERFACE
MULTIFUNCTION GENERAL PURPOSE I/O PORTS
TQFP100 Power with Slug Down
DESCRIPTION
The TDA7500 is an integrated circuit implement-
ing a fully digital, integrated and advanced solu-
tion to perform the signal processing in front of
the power amplifier and behind the AM/FM tuner
or any other audio sources. The chip integrates
two 43 MIPs DSP cores: one for stereo decoding,
noise blanking, weak signal processing and multi-
BLOCK DIAGRAM
analog audio in
AM-IF
CC
CD
tel,navi
AM/FM lev.
AM/FM mpx
RDS mpx
1
2
3
4
2
3
1
Mute
supply Cref
22
3
Input Multiplexer,
Analog Level Adjust
AM
Noise
Detector
IIC
2 channel analog bypass
4
VDD GND
CODEC-ref
32
VS SigGnd RefOut
Output Analog Volume Control,
select. Line Driver
6 signal/line out
DAC-ref 6
Σ∆ Modulator
Σ∆ Modulator
Σ∆ Modulator
Σ∆ Modulator
Decimation
Filter
Decimation
Filter
uP control
Main micro
(4
I/O's)4
Display uP (4 I/O's)
Spectrum Analyser 4
CLK in Audio Bus Synch.
8.55MHz
Data, ctl
8+3
128k (4M) x 8
Address (1 I/O)
17
Audio Bus 6 ch.
dig. aud. out (2 I/O's)
clkt, wst, clkr, wsr
dig. aud. in (2 I/O's)
3
4
2
CD input
CDC input
MD input
IIC / SPI
SPI
XTAL Osc.,
PLL
Ext. Memory
Interface
Serial Audio
Interface
SPDIF
Interface
Mux
Exchange
Interface
1 stereo channel
Sample Rate
Converter
RDS bit/blk Int.(1 I/O)
RDS (4 I/O's) 4
Error corrected RDS blocks
alternatively:
RDS clk, dat, qual, ARI
SPI
RDS
Grp & blk
sync., error Demod. RDS
correction
Filter
Voltage
Ref.
Codec
Ctl Reg.
Test I/F
Oversampling
Filter
Oversampling
Filter
Oversampling
Filter
Noise
Shaper
Noise
Shaper
Noise
Shaper
SC Filter
SC Filter
SC Filter
SC Filter
SC Filter
SC Filter
X bus 1 X Register
Ram 512
Y Register
Ram 512
Program
Ram 1024
Rom 256
DSP Orpheus Core
including 12 GPIO• s
FM processing,
AM processing,
Traffic mem., Dolby,
Speech synth., etc...
Debug, Test Interface
DSP1
X bus 0 X Register
Ram 512
Y Register
Ram 512
Program
Ram 5632
Rom 256
DSP Orpheus Core
including 12 GPIO• s
Audio processing,
Sound processing
Debug, Test Interface
DSP0
Int
Reset
5
5
VDD
GND
2 Test
4
4
(3 I/O's)
(3 I/O's)
September 1999
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/14
1 page  
TDA7500
PIN DESCRIPTION (continued)
N°
39 SRA<2>
NAME
40 SRA<3>
41 SRA<4>
42 SRA<5>
43 SRA<6>
44 SRA<7>
45 SRA<8>
46 SRA<9>
47 SRA<10>
48 SRA<11>
49 SRA<12>
50 CGND2
51 CVDD2
52 SRA<13>
53 SRA<14>
54 SRA<15>
55 SRA<16>/DSP0_GPIO8
56 DWR
57 DRD
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
DSP SRAM Address Line<2> (Output)/DSP DRAM Address
Line<2> (Output). This pin act as the EMI address line 2 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<3> (Output)/DSP DRAM Address
Line<3> (Output). This pin act as the EMI address line 3 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<4> (Output)/DSP DRAM Address
Line<4> (Output). This pin act as the EMI address line 4 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<5> (Output)/DSP DRAM Address
Line<5> (Output). This pin act as the EMI address line 5 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<6> (Output)/DSP DRAM Address
Line<6> (Output). This pin act as the EMI address line 6 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<7> (Output)/DSP DRAM Address
Line<7> (Output). This pin act as the EMI address line 7 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<8> (Output)/DSP DRAM Address
Line<8> (Output). This pin act as the EMI address line 8 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<9> (Output)/DSP DRAM Address
Line<9> (Output). This pin act as the EMI address line 9 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<10> (Output)/DSP DRAM Address
Line<10> (Output). This pin act as the EMI address line 10 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<11> (Output)/DSP DRAM Address
Line<11> (Output). This pin act as the EMI address line 11 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<12> (Output)/DSP DRAM Address
Line<12> (Output). This pin act as the EMI address line 12 in both
SRAM Mode and DRAM Mode.
Ground pin dedicated to the digital core part.
Supply pin dedicated to the digital core part.
DSP SRAM Address Line<13> (Output)/DSP DRAM Address
Line<13> (Output). This pin act as the EMI address line 13in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<14> (Output)/DSP DRAM Address
Line<14> (Output). This pin act as the EMI address line 14 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<15> (Output)/DSP DRAM Address
Line<15> (Output). This pin act as the EMI address line 15 in both
SRAM Mode and DRAM Mode.
DSP SRAM Address Line<16> (Output)/DSP DRAM Address
Line<16> (Output)/General Purpose I/O (Input/Output). This pin
acts as the EMI address line 16 in both SRAM Mode and DRAM
Mode. Optionally it can be used as general purpose I/O controlled
by DSP0.
DSP SRAM Write Enable (Output)/DRAM Write Enable (Output).
This pin serves as the write enable for the EMI in both DRAM and
SRAM Mode.
DSP SRAM Read Enable(Output)/DRAM Read Enable (Output).
This pin serves as the read enable for the EMI in both DRAM and
SRAM Mode.
5/14
5 Page 
TDA7500
Every component hooked up to the I2C bus has
its own unique address whether it is a CPU,
memory or some other complex function chip.
Each of these chips can act as a receiver and /or
transmitter on its functionality.
General Purpose Input/Output
The DSP requires a set of external general pur-
pose input/output lines, and a reset line. These
signals are used by external devices to signal
events to the DSP. The GPIO lines are imple-
mented as DSP ’s peripherals. The GPIO lines
are grouped in Port A which is connected to DSP
0, and Port B, which is connected to DSP1.
PLL Clock Oscillator
The PLL Clock Oscillator can accept an external
clock at XTI or it can be configured to run an in-
ternal oscillator when a crystal is connected
across pins XTI & XTO. There is an input divide
block IDF (1 -> 32) at the XTI clock input and a
multiply block MF (9 -> 128) in the PLL loop.
Hence the PLL can multiply the external input
clock by a ratio MF/IDF to generate the internal
clock. This allows the internal clock to be within 1
MHz of any desired frequency even when XTI is
much greater than 1 MHz. It is recommended that
the input clock is not divided down to less than 1
MHz as this reduces the Phase Detector’s update
rate.
The clocks to the DSP can be selected to be
either the VCO output divided by 2 to 16, or be
driven by the XTI pin directly.
The crystal oscillator and the PLL will be gated off
when entering the power-down mode (by setting
a register on DSP0).
Codec
The CODEC is composed of four AD mono con-
verters, three DA stereo converters. The ADC
can operate both in audio mode and in FM/AM
mode. When in audio mode, it converts the audio
bandwidth from 20 to 20KHz. The A to D is a third
order Sigma-Delta converter, the converter reso-
lutions is 20 bit with 93 dB of dynamic range and
85dB of total harmonic distortion. When in FM
mode, the converted bandwidth is up to 192KHz.
The D to A is a third order Sigma-Delta converter
with a low noise reconstructing analog filter, the
converter resolution is 20 bit with 93 dB of dy-
namic range and 85dB of total harmonic distor-
tion. All the reference voltages are generated in-
side the chip.
Some capabilities of the CODEC are listed below:
20-Bit Resolution
Digital Anti-Alias Filtering embedded
Adjustable System Sampling Rates
93dB D/A Dynamic Range (A-Weighted)
93dB A/D Dynamic Range (A-Weighted)
85dB D/A (THD+N/S)
85dB A/D (THD+N/S)
Internal Differential Analog Architecture
+3.3V Power Supply
SOFTWARE FEATURES
A great flexibility is guaranteed by the two program-
mable DSP cores. A list of the main software func-
tions which can be implemented in the TDA7500 is
enclosed hereafter. A block diagram of the audio
processing flow is shown in Fig. 1 below.
AM/FM Baseband Signal Processing
FM weak signal processing
Integrated 19 kHz MPX filter and deemphasis
flexible noise cancellation
flexible multipath detector
Generic Audio Signal Processsing
Loudness
Bass, treble, fader control
Volume control
Distortion Limiting
Premium Equalization
Soft mute
TAPE Signal Processsing
Dolby B Noise Reduction
Automatic Music Search
CD Signal Proceessing
Dynamic Range Compression
Audiophile (optional)
Parametric Equalization
Crossover Patters
Channel Delays
Center Channel Imaging Output
Audio Noise Reduction
Application Scheme
The TDA7500 can operate as a standalone de-
vice either it can interface the TDA7501 which
contains the analog input multiplexer, analog vol-
ume control and the line-driver. The FM_MPX
and FM_LEVEL signals coming from the tuner
and other signals supplied by analog sources are
adapted by the TDA7501 and fed to the
TDA7500. A block diagram of the system is
shown in Fig.2 below.
The TDA7500 converts all the analog signals into
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet TDA7500.PDF ] | |
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