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PDF TDA7435D Data sheet ( Hoja de datos )

Número de pieza TDA7435D
Descripción DIGITALLY CONTROLLED AUDIO PROCESSOR WITH LOUDSPEAKERS EQUALIZER
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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TDA7435
DIGITALLY CONTROLLED AUDIO PROCESSOR
WITH LOUDSPEAKERS EQUALIZER
INPUT
- FOUR HIGH PASS CHANNELS
- TWO AUX STEREO CHANNELS
VOLUME CONTROL IN 1dB STEPS WITH
GAIN UP TO 15dB
SOFT MUTE AND DIRECT MUTE
FOUR AUXILIARY CHANNELS:
- TWO SPEAKERS CONTROL IN 1dB STEP
- TWO CHANNELS MULTIPLEXED WITH
THE HIGH PASS CHANNELS
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DESCRIPTION
The audioprocessor TDA7435 is an upgrade of
the TDA731X audioprocessor family.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained.
SO28
ORDERING NUMBER: TDA7435D
A second programmable high pass filtering pro-
vides the loudspeakers equalization.
The soft Mute function is implemented andcan be
activated in two ways:
1 Via serial bus (Mute byte, bit D0)
2 Directly on pin 3 through an I/O line of the mi-
crocontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
BLOCK DIAGRAM
HP FL 1
HP FL 2
HP FR 1
HP FR 2
HP RL 1
HP RL 2
HP RR 1
HP RR 2
AUX 2 IN L
AUX 2 IN R
22
21
20
19
18
17
16
15
6
7
HP FILTER
HP FILTER
HP FILTER
HP FILTER
AUX 1 IN L
AUX 1 IN R
1
2
GAIN
0-15dB/1dB step
CSM
3
SOFT
MUTE
SDA SCL DGND AGND CREF VCC
27 26 25 24 23 28
I2C BUS
SUPPLY
12
OUT REF
MUX
ATTENUATOR
0/-79dB
ATTENUATOR
0/-79dB
10
HP FL OUT
11
HP FR OUT
13
HP RL OUT
14
HP RR OUT
9
AUX 2 OUT L
8
AUX 2 OUT R
5
AUX 1 OUT L
4
AUX 1 OUT R
November 1996
D96AU437A
1/10

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TDA7435D pdf
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7435 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 2, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.3 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
Figure 2: Data Validity on the I2CBUS
TDA7435
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 4). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception
of each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In this
case the master transmitter can generate the
STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 3: Timing Diagram of I2CBUS
Figure 4: Acknowledge on the I2CBUS
5/10

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