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PDF P80C31X2 Data sheet ( Hoja de datos )

Número de pieza P80C31X2
Descripción 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V/ low power/ high speed 30/33 MHz
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
80C31X2/32X2
80C51X2/52X2/54X2/58X2
87C51X2/52X2/54X2/58X2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP
128B/256B RAM
low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
Preliminary data
2001 Sep 24
Philips
Semiconductors

1 page




P80C31X2 pdf
Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Preliminary data
80C3xX2; 80C5xX2;
87C5xX2
PART NUMBER DERIVATION
Memory
P87C51X2
7 = OTP
0 = ROM or
ROMless
5 = ROM/OTP
3 = ROMless
1 = 128 BYTES RAM
4 KBYTES ROM/OTP
2 = 256 BYTES RAM
8 KBYTES ROM/OTP
4 = 256 BYTES RAM
16 KBYTES ROM/OTP
8 = 256 BYTES RAM
32 KBYTES ROM/OTP
Temperature Range
B = 0 °C TO +70 °C
F = –40 °C TO +85 °C
Package
A = PLCC
N = DIP
The following table illustrates the correlation between operating mode, power supply and maximum external clock frequency:
Operating Mode
Power Supply
Maximum Clock Frequency
6-clock
5 V ± 10%
30 MHz
6-clock
2.7 V to 5.5 V
16 MHz
12-clock
5 V ± 10%
33 MHz
12-clock
2.7 V to 5.5 V
16 MHz
2001 Sep 24
5

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P80C31X2 arduino
Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Preliminary data
80C3xX2; 80C5xX2;
87C5xX2
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. However, minimum and
maximum high and low times specified in the data sheet must be
observed.
Reset
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (24 oscillator periods in 12-clock and 12
oscillator periods in 6-clock mode), while the oscillator is running. To
insure a reliable power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. After the reset, the part runs
in 12-clock mode.
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
Idle Mode
In idle mode (see Table 2), the CPU puts itself to sleep while all of
the on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0 V and care must be taken to return VCC to
the minimum specified operating voltages before the Power Down
Mode is terminated.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values. WUPD (AUXR1.3–Wakeup from
Power Down) enables or disables the wakeup from power down with
external interrupt. Where:
WUPD = 0: Disable
WUPD = 1: Enable
To properly terminate Power Down, the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
To terminate Power Down with an external interrupt, INT0 or INT1
must be enabled and configured as level-sensitive. Holding the pin
low restarts the oscillator but bringing the pin back high completes
the exit. Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the instruction that put
the device into Power Down.
Low-Power EPROM operation (LPEP)
The EPROM array contains some analog circuits that are not
required when VCC is less than 4 V, but are required for a VCC
greater than 4 V. The LPEP bit (AUXR.4), when set, will powerdown
these analog circuits resulting in a reduced supply current. This bit
should be set ONLY for applications that operate at a VCC less than
4 V.
Design Consideration
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by
reset, the instruction following the one that invokes Idle should not
be one that writes to a port pin or to external memory.
ONCEMode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked in the following way:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Table 2. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
Idle
Internal
1 1 Data
Idle
External
1 1 Float
Power-down
Internal
0 0 Data
Power-down
External
0 0 Float
PORT 1
Data
Data
Data
Data
PORT 2
Data
Address
Data
Data
PORT 3
Data
Data
Data
Data
2001 Sep 24
11

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