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PDF TYN808RG Data sheet ( Hoja de datos )

Número de pieza TYN808RG
Descripción 8A SCRs
Fabricantes STMicroelectronics 
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®
SENSITIVE & STANDARD
TN8, TS8 and TYNx08 Series
8A SCRs
MAIN FEATURES:
Symbol
IT(RMS)
VDRM/VRRM
Value
8
600 to 1000
Unit
A
V
A
G
K
A
A
IGT
0.2 to 15
mA
DESCRIPTION
Available either in sensitive (TS8) or standard
(TN8 / TYN) gate triggering levels, the 8A SCR
series is suitable to fit all modes of control, found
in applications such as overvoltage crowbar
protection, motor control circuits in power tools
and kitchen aids, inrush current limiting circuits,
capacitive discharge ignition and voltage
regulation circuits...
Available in through-hole or surface-mount
packages, they provide an optimized performance
in a limited space area.
ABSOLUTE RATINGS (limiting values)
KA
G
DPAK
(TS8-B)
(TN8-B)
A
K
AG
TO-220AB
(TS8-T)
KA
G
IPAK
(TS8-H)
(TN8-H)
A
K
A
G
TO-220AB
(TYNx)
Symbol
Parameter
Value
Unit
IT(RMS)
IT(AV)
RMS on-state current (180° conduction angle)
Average on-state current (180° conduction angle)
ITSM
I²t
dI/dt
IGM
PG(AV)
Tstg
Tj
VRGM
Non repetitive surge peak on-state
current
I²t Value for fusing
Critical rate of rise of on-state current
IG = 2 x IGT , tr 100 ns
tp = 8.3 ms
tp = 10 ms
tp = 10 ms
F = 60 Hz
Peak gate current
tp = 20 µs
Average gate power dissipation
Storage junction temperature range
Operating junction temperature range
Maximum peak reverse gate voltage (for TN8 & TYN only)
Tc = 110°C
8
Tc = 110°C
5
Tj = 25°C
TS8/TN8 TYN
73 100
70 95
Tj = 25°C
24.5 45
A
A
A
A2S
Tj = 125°C
50
A/µs
Tj = 125°C
Tj = 125°C
4
1
- 40 to + 150
- 40 to + 125
5
A
W
°C
V
April 2002 - Ed: 4A
1/9

1 page




TYN808RG pdf
TN8, TS8 and TYNx08 Series
Fig. 3-2: Relative variation of thermal impedance
junction to ambient versus pulse duration
(recommended pad layout, FR4 PC board for
DPAK).
Fig. 4-1: Relative variation of gate trigger current
and holding current versus junction temperature
for TS8 series.
K = [Zth(j-a)/Rth(j-a)]
1.00
0.10
DPAK
TO-220AB
0.01
1E-2
1E-1
tp(s)
1E+0
1E+1
1E+2 5E+2
Fig. 4-2: Relative variation of gate trigger current
and holding current versus junction temperature
for TN8 & TYN series.
IGT,IH,IL [Tj] / IGT ,IH,IL [Tj = 25 °C]
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40
IGT
-20 0
IH & IL
Rgk = 1k
Tj(°C)
20 40 60 80 100 120 140
Fig. 5: Relative variation of holding current
versus gate-cathode resistance (typical values)
for TS8 series.
IGT,IH,IL [Tj] / IGT ,IH,IL [Tj = 25 °C]
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40
IGT
-20 0
Tj(°C)
20 40 60 80
IH & IL
100 120 140
IH[Rgk] / IH[Rgk = 1k]
Rgk(k)
Fig. 6: Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
for TS8 series.
dV/dt[Rgk] / dV/dt [Rgk = 220]
Rgk(k)
Fig. 7: Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical values)
for TS8 series.
dV/dt[Cgk] / dV/dt [Rgk = 220 ]
15.0
VD = 0.67 x VDRM
Tj = 125°C
12.5
Rgk = 220
10.0
7.5
5.0
2.5
0.0
0
Cgk(nF)
20 40 60 80 100 120 140 160 180 200 220
5/9

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