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PDF TYN612 Data sheet ( Hoja de datos )

Número de pieza TYN612
Descripción SENSITIVE & STANDARD(12A SCRs)
Fabricantes STMicroelectronics 
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TYN612 Hoja de datos, Descripción, Manual
®
SENSITIVE & STANDARD
TN12, TS12 and TYNx12 Series
12A SCRs
MAIN FEATURES:
Symbol
Value
Unit
IT(RMS)
12 A
VDRM/VRRM
600 to 1000
V
IGT
0.2 to 15
mA
DESCRIPTION
Available either in sensitive (TS12) or standard
(TYN, TN12...) gate triggering levels, the 12A SCR
series is suitable to fit all modes of control found in
applications such as overvoltage crowbar
protection, motor control circuits in power tools
and kitchen aids, in-rush current limiting circuits,
capacitive discharge ignition, voltage regulation
circuits...
Available in though-hole or surface-mount
packages, they provide an optimized performance
in a limited space area.
A
G
K
A
A
KA
G
DPAK
(TS12-B)
(TN12-B)
A
KA
G
D2PAK
(TN12-G)
A
KA
G
IPAK
(TS12-H)
(TN12-H)
K
A
G
TO-220AB
(TYN)
ABSOLUTE RATINGS (limiting values)
Symbol
IT(RMS)
IT(AV)
Parameter
RMS on-state current (180° conduction angle)
Average on-state current (180° conduction angle)
Tc = 105°C
Tc = 105°C
ITSM
It
dI/dt
IGM
PG(AV)
Tstg
Tj
VRGM
Non repetitive surge peak
on-state current
tp = 8.3 ms
tp = 10 ms
I t Value for fusing
Critical rate of rise of on-state
current IG = 2 x IGT , tr 100 ns
Peak gate current
tp = 10 ms
F = 60 Hz
tp = 20 µs
Average gate power dissipation
Storage junction temperature range
Operating junction temperature range
Maximum peak reverse gate voltage (for TN12 & TYN)
Tj = 25°C
Tj = 25°C
Tj = 125°C
Tj = 125°C
Tj = 125°C
Value
Unit
12
8
DPAK /
IPAK
115
110
60
D PAK /
TO-220AB
146
140
98
A
A
A
AS
50 A/µs
4
1
- 40 to + 150
- 40 to + 125
5
A
W
°C
V
September 2000 - Ed: 3
1/10

1 page

TYN612 pdf
TN12, TS12 and TYNx12 Series
Fig. 3-2: Relative variation of thermal
impedance junction to ambient versus pulse
duration (recommended pad layout, FR4 PC
board).
K = [Zth(j-a)/Rth(j-a)]
1.00
0.10
DPAK
D2PAK
TO-220AB
0.01
1E-2
1E-1
tp(s)
1E+0 1E+1
1E+2 5E+2
Fig. 4-1: Relative variation of gate trigger
current, holding current and latching versus
junction temperature for TS12 series.
IGT,IH,IL [Tj] / IGT,IH,IL [Tj = 25°C]
2.0
1.8
IGT
1.6
1.4
1.2
1.0
IH & IL
Rgk = 1k
0.8
0.6
0.4
0.2
0.0
-40 -20
0
Tj(°C)
20 40 60 80 100 120 140
Fig. 4-2: Relative variation of gate trigger
current, holding current and latching current
versus junction temperature for TN12 & TYN
series.
IGT,IH,IL [Tj] / IGT,IH,IL [Tj = 25°C]
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40
IGT
-20
0
Tj(°C)
20 40 60 80
IH & IL
100 120 140
Fig. 6: Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
for TS12 series.
dV/dt[Rgk] / dV/dt [Rgk = 220]
10.0
Tj = 125°C
VD = 0.67 x VDRM
1.0
Rgk(k)
0.1
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Fig. 5: Relative variation of holding current
versus gate-cathode resistance (typical values)
for TS12 series.
IH[Rgk] / IH[Rgk = 1k]
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1E-2
Rgk(k)
1E-1
1E+0
Tj = 25°C
1E+1
Fig. 7: Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical values)
for TS12 series.
dV/dt[Cgk] / dV/dt [Rgk = 220]
4.0
VD = 0.67 x VDRM
3.5 Tj = 125°C
Rgk = 220
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
Cgk(nF)
25 50 75 100 125 150
5/10

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