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PDF UT8CR512K32-17VPX Data sheet ( Hoja de datos )

Número de pieza UT8CR512K32-17VPX
Descripción UT8CR512K32 16 Megabit SRAM
Fabricantes Aeroflex Circuit Technology 
Logotipo Aeroflex Circuit Technology Logotipo



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No Preview Available ! UT8CR512K32-17VPX Hoja de datos, Descripción, Manual

Standard Products
UT8CR512K32 16 Megabit SRAM
Advanced Data Sheet
October 2004
www.aeroflex.com/4MSRAM
FEATURES
‰ 17ns maximum access time
‰ Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
‰ CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
‰ Radiation performance
- Intrinsic total-dose: 300 Krad(Si)
- SEL Immune >100 MeV-cm2/mg
- LETth (0.25): 53.0 MeV-cm2/mg
- Memory Cell Saturated Cross Section 1.67E-7cm2/bit
- Neutron Fluence: 3.0E14n/cm2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup 1.0E11 rad(Si)/sec
‰ Packaging options:
- 68-lead ceramic quad flatpack (20.238 grams with lead
frame)
‰ Standard Microcircuit Drawing 5962-04227
- QML compliant part
INTRODUCTION
The UT8CR512K32 is a high-performance CMOS static RAM
multi-chip module (MCM), organized as four individual
524,288 words by 8 bit SRAMs with common output enable.
Easy memory expansion is provided by active LOW chip
enables (EN), an active LOW output enable (G), and three-state
drivers. This device has a power-down feature that reduces
power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking the
corresponding chip enable (En) input LOW and write enable
(Wn) input LOW. Data on the I/O pins is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
W3
E3
W2
E2
W1
E1
W0
E0
A(18:0)
G
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
Figure 1. UT8CR512K32 SRAM Block Diagram
DQ(7:0)
or
DQ0(7:0)
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UT8CR512K32-17VPX pdf
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(-55°C to +125°C for (C) screening and -40°C to 125°C for (W) screening)
SYMBOL
PARAMETER
CONDITION
VIH High-level input voltage
VIL Low-level input voltage
VOL1 Low-level output voltage
IOL = 8mA,VDD2 =VDD2 (min)
VOH1 High-level output voltage
IOH = -4mA,VDD2 =VDD2 (min)
CIN1 Input capacitance
ƒ = 1MHz @ 0V
CIO1 Bidirectional I/O capacitance ƒ = 1MHz @ 0V
IIN Input leakage current
VIN = VDD2 and VSS
IOZ Three-state output leakage VO = VDD2 and VSS, VDD2 = VDD2 (max)
current
G = VDD2 (max)
IOS2, 3
Short-circuit output current
VDD2 = VDD2 (max), VO = VDD2
VDD2 = VDD2 (max), VO = VSS
MIN
.7*VDD2
.8*VDD2
MAX
UNIT
V
.3*VDD2
.2*VDD2
V
V
V
12 pF
12 pF
-2 2 µA
-2 2 µA
-100 +100 mA
IDD1(OP1) Supply current operating
@ 1MHz
IDD1(OP2) Supply current operating
@66MHz
IDD2(OP1) Supply current operating
@ 1MHz
IDD2(OP2) Supply current operating
@66MHz
IDD1(SB)4
Supply current standby @
0Hz
IDD2(SB)4
IDD1(SB)4
Supply current standby
A(18:0) @ 66MHz
IDD2(SB)4
Inputs : VIL = VSS + 0.2V
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
Inputs : VIL = VSS + 0.2V,
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
Inputs : VIL = VSS + 0.2V
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
Inputs : VIL = VSS + 0.2V,
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
CMOS inputs , IOUT = 0
EN = VDD2 -0.2
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
CMOS inputs , IOUT = 0
EN = VDD2 - 0.2
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. VIH = VDD2 (max), VIL = 0V.
45 mA
93 mA
243 µA
12 mA
38 mΑ
100 µA
38 mΑ
100 µA
5

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UT8CR512K32-17VPX arduino
DATA RETENTION CHARACTERISTICS (Pre-Radiation)3 (VDD2 = VDD2 (min), 1 Sec DR Pulse)
SYMBOL
PARAMETER
MINIMUM MAXIMUM UNIT
VDR VDD1 for data retention
IDDR 1
Data retention current
Device Type 1
1.0
-55°C
25°C
125°C
1.0
--
-- V
600 µA
600 µA
30 mA
IDDR 1
Data retention current
Device Type 2
-40°C
25°
125°C
--
600 µA
600 µA
30 mA
tEFR1,2
Chip deselect to data retention time
00
ns
tR1,2 Operation recovery time
tAVAV
tAVAV
ns
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. EN = VDD2 all other inputs = VDD2 or VSS
2. VDD2 = 0 volts to VDD2 (max)
VDD1
1.7V
DATA RETENTION MODE
VDR > 1.0V
1.7V
VIN >0.7VDD2 CMOS
EN
VIN <0.3VDD2 CMOS
tEFR
VSS
VDD2
tR
Figure 5. Low VDD Data Retention Waveform
188 ohms
1.4V
CMOS
VDD2-0.05V
0.0V
90%
10%
50pF
< 2ns
Input Pulses
Notes:
1. 50pF including scope probe and test socket.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD2/2).
Figure 6. AC Test Loads and Input Waveforms
< 2ns
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