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PDF UT80C196 Data sheet ( Hoja de datos )
| Número de pieza | UT80C196 | |
| Descripción | UT80C196KD Microcontroller | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT80C196KD Microcontroller
Datasheet
September 2002
FEATURES
q 20MHz 16-bit Microcontroller compatible with Industry
Standard’s MCS-96 ISA
- Register to Register Architecture
- 1000 Byte Register RAM
q Three 8-bit I/O Ports
q On-board Interrupt Controller
q Three Pulse-Width Modulated Outputs
q High Speed I/O
q UART Serial Port
q Dedicated Baud Rate Generator
q Software and Hardware Timers
- 16-Bit Watchdog Timer, Four 16-Bit Software Timers
- Three 16-Bit Counter/Timers
q Error detection and correction for external memory accesses
q QML Q compliant part
q Standard Microcircuit Drawing 5962-98583
INTRODUCTION
The UT80C196KD is compatible with industry standard’s
MCS-96 instruction set. The UT80C196KD is supported by
commercial hardware and software development tools.
The UT80C196KD accesses instruction code and data via a
16-bit address and data bus. The 16-bit bus allows the
microcontroller to access 128K bytes of instruction/data
memory. Integrated software and hardware timers, high speed
I/O, pulse width modulation circuitry, and UART make the
UT80C196KD ideal for control type applications. The CPU’s
ALU supports byte and word adds and subtracts, 8 and 16 bit
multiplies, 32/16 and 16/8 bit divides, as well as increment,
decrement, negate, compare, and logical operations. The
UT80C196KD’s interrupt controller prioritizes and vectors 18
interrupt events. Interrupts include normal interrupts and
special interrupts. To reduce power consumption, the
microcontroller supports software invoked idle and power
down modes.
The UT80C196KD is packaged in a 68-lead quad flatpack.
1000 Bytes
RAM
Register File
ALU
CPU
MicroCode
Engine
Interrupt
Controller
PTS
Memory
Controller
Queue
Control
Signals
Address /Data Bus
Watchdog
Timer
PWM
Serial
Port
HSIO and
Timers
Alternate
Functions
PORT0
Alternate
Functions
PORT2
HSI HSO
EXTINT
PORT1
Figure 1. UT80C196KD Microcontroller
ECB0-
ECB5
HOLD
HLDA
BREQ
PWM1
PWM2
1 page  
Notes:
1. The Unimplemented Opcode and Software Trap interrupts are not prioritized. The Interrupt Controller immediately services these interrupts when they are
asserted. NMI has the highest priority of all prioritized interrupts. Any PTS interrupt has priority over lower priority intterupts, and over all other maskable
interrupts. The standard maskable interrupts are serviced according to their priority number with INT0 has the lowest priorityof all interrupts.
2. These interrupts can be configured to function as independant, external interrupts.
3. If the Serial interrupt is masked and the Receive and Transmit interrupts are enabled, the RI flag and TI flag generate separate Receive and Transmit inter-
rupts.
4. If the Receive and Transmit interrupts are masked and the Serial interrupt is enabled, both RI flag and TI flag generate a Serial Port interrupt.
5
5 Page 
UT80C196KD
Bus Control
UT80C196 KD
Bus Control
AD0-AD15
16-Bit
Multiplexed
Address/Data
AD8-AD15
8-Bit
Latched
Address High
AD0-AD7
8-Bit
Multiplexed
Address/Data
16-Bit Bus
Figure 2. Bus Width Options
8-Bit Bus
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UT80C196.PDF ] | |
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