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PDF UT62256CSC-35L Data sheet ( Hoja de datos )

Número de pieza UT62256CSC-35L
Descripción 32K X 8 BIT LOW POWER CMOS SRAM
Fabricantes ETC 
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No Preview Available ! UT62256CSC-35L Hoja de datos, Descripción, Manual

Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
FEATURES
GENERAL DESCRIPTION
Access time : 35/70ns (max.)
Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 3mA (typical) normal
2uA (typical) L-version
1uA (typical) LL-version
Single 5V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mmx13.4mm STSOP
The UT62256C is a 262,144-bit low power
CMOS static random access memory
organized as 32,768 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
The UT62256C is designed for high-speed
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.
The UT62256C operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
A4
A3
A14 .
.A13 ROW
A12 DECODER
A7
A6 .
A5
A8
I/O1
...
... I/O
CONTROL
I/O8
...
MEMORYARRAY
512 ROWS × 512 COLUMNS
. ..
COLUMNI/O
COLUMNDECODER
VCC
VSS
CE LOGIC
WE CONTROL
OE
A10 A9 A11 A2 A1 A0
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
28 Vcc
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
PDIP/SOP
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 UT62256C 21
9 20
10 19
11 18
12 17
13 16
14 15
STSOP
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1

1 page




UT62256CSC-35L pdf
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
Address
CE
WE
DOUT
DIN
tAS
(4)
tWC
tAW
tCW
tWP
tWHZ
High-Z
tWR
tOW
tDW tDH
Data Valid
(4)
WRITE CYCLE 2 ( CE Controlled) (1,2,5)
Address
CE
WE
DOUT
tWC
tAW
tAS tCW
tWP
tWHZ
(4)
DIN
tWR
High-Z
tDW tDH
Data Valid
Notes :
1. WE or CE must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after WE LOW transition, the
outputs remain in a high impedance state.
6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5

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UT62256CSC-35L arduino
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
REV. 0.9
REV. 1.0
DESCRIPTION
1. Original.
1. The test condition of ICC1 and ICC2 have been revised.
2. The symbols CE#,OE# and WE# are revised as
CE , OE and WE
3. The ordering information of PACKAGE ,STSOP-1 is
revised as STSOP.
DATE
Apr. 26,2001
MAY. 14,2001
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11

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