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PDF USBDFXXW5 Data sheet ( Hoja de datos )

Número de pieza USBDFXXW5
Descripción EMI FILTER AND LINE TERMINATION FOR USB DOWNSTREAM PORTS
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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®
A.S.D.
USBDFxxW5
EMI FILTER AND LINE TERMINATION
FOR USB DOWNSTREAM PORTS
APPLICATIONS
EMI Filter and line termination for USB down-
stream ports on:
- Desktop computer
- Notebooks
- Workstations
- USB Hubs
FEATURES
n Monolithic device with recommended line termi-
nation for USB downstream ports
n Integrated Rt series termination and Ct bypass-
ing capacitors.
n Integrated ESD protection
n Small package size
DESCRIPTION
The USB specification requires USB
downstream ports to be terminated with
pull-down resistors from the D+ and D- lines to
ground. On the implementation of USB
systems, the radiated and conducted EMI
should be kept within the required levels as
stated by the FCC regulations. In addition to
the requirements of termination and EMC
compatibility, the computing devices are
required to be tested for ESD susceptibility.
The USBDFxxW5 provides the recommended line
termination while implementing a low pass filter to
limit EMI levels and providing ESD protection
which exceeds IEC 61000-4-2 level 4 standard.
The device is packaged in a SOT323-5L which is
the smallest available lead frame package (50%
smaller than the standard SOT23).
BENEFITS
n EMI / RFI noise suppression
n Required line termination for USB downstream
ports
n ESD protection exceeding IEC61000-4-2 level 4
n High flexibility in the design of high density
boards
n Tailored to meet USB 1.1 standard
TM: ASD and TRANSIL are a trademarks of STMicroelectronics.
May 2000 Ed : 1C
SOT323-5L
FUNCTIONAL DIAGRAM
D+ In
Gnd
D- In
Rt
Ct Rd
Ct Rd
Rt
Code 01
Code 02
Tolerance
Rt
33
15
±10%
Rd
15k
15k
±10%
D+ Out
D- Out
Ct
47pF
47pF
±20%
1/9

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USBDFXXW5 pdf
Fig. A4: USBDFxxW5 ESD clamping behavior
USBDFxxW5
VPP
ESD Surge
Rg S1 R S2
Rd Vinput
Rd
VBR
Voutput
VBR
USBDFxxW5
Rload
Device
to be
protected
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical
dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and
Rload>Rd, it gives these formulas:
Vinput = Rg.VBR + Rd.Vg
Rg
Voutput = Rt.VBR + Rd.Vinput
Rt
The results of the calculation done for VPP=8kV, Rg=330(IEC61000-4-2 standard), VBR=7V (typ.)
and Rd = 1(typ.) give:
Vinput = 31.2 V
Voutput = 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low
current involved after the resistance R.
The measurements done here after show very clearly (Fig. A6) the high efficiency of the ESD protection :
- no influence of the parasitic inductances on Vout stage
- output clamping voltage very close to VBR (positive strike) and -VF (negative strike)
Fig. A5: Measurement board
ESD
SURGE
16kV
Air
Discharge
TEST BOARD
Vin Vout
5/9

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