PDF UPD98405 Data sheet ( Hoja de datos )

Número de pieza	UPD98405
Descripción	155M ATM INTEGRATED SAR CONTROLLER
Fabricantes	NEC
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No Preview Available ! DATA SHEET MOS INTEGRATED CIRCUIT µPD98405 155M ATM INTEGRATED SAR CONTROLLER DESCRIPTION The µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and has the functions of the AAL-5 SAR sublayer, ATM layer, and TC sublayer. FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz) • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions • Hardware support of AAL-5 processing • Software support of non-AAL-5 traffic • SONET STS-3c/SDH STM-1 155-Mbps framer function • Clock recovery/clock synthesizer function • Supports up to 32 K virtual channels (VCs) • Sixteen traffic shapers for VBR for transmission scheduling • Hardware support of CBR/VBR/ABR/UBR service • Supports multi-cell burst transfer for transmission and reception • MIB counter function • Supports LAN emulation function • Receive FIFO of 96 cells • External PHY devices connectable: UTOPIA Level-1 interface • 0.35-µm CMOS process, +5-/3.3-V power supply - Bus interface +5 V: +5-/3.3-V power supply - Bus interface +3.3 V: +3.3-V power supply • 304-pin plastic QFP ORDERING INFORMATION Part Number µPD98405GL-PMU Package 304-pin plastic QFP (0.5-mm fine pitch) (40 × 40 mm) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12689EJ2V0DS00 (2nd edition) Date Published April 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1997, 1999 1 page µPD98405 PIN NAME ABRT_B : Abort ACK64_B : Acknowledge 64-bit Transfer AD63-AD0 : Address/Data AGND : Ground for Analog Part ASEL_B : Slave Address Select ATTN_B : Attention AVDD3 : +3.3 V Power Supply for Analog Part BE3_B-BE0_B : Byte Enable CA18-CA0 : Control Memory Address CBE3_B-CBE0_B : Local Port Byte Enable CD31-CD0 : Control Memory Data CLK : Clock COE_B : Control Memory Output Enable CPAR3-CPAR0 : Control Memory parity CWE_B : Control Memory Write Enable DEVSEL_B : Device Select DR/W_B : DMA Read/Write EMPTY_B/RCLAV : PHY Empty/Rx Cell Available ERR_B : Error E2PCLK : Clock for EEPROM E2PCS : EEPROM Chip Select E2PDI : Serial Data Input from EEPROM E2PDO : Serial Data Output to EEPROM FRAME_B : Cycle Frame FULL_B/TCLAV : PHY Buffer full/Tx Cell Available GND : Ground for Digital Part GNT_B : Grant HGND : Ground for High-Speed Part HVDD3 : +3.3 V Power Supply for High-Speed Part IDSEL : ID Select INITD : Initialization Disable INTR_B : Interrupt IRDY_B : Initiator Ready JCK : JTAG Test Pin JDI : JTAG Test Pin JDO : JTAG Test Pin JMS : JTAG Test Pin JRST_B : JTAG Test Pin OE_B : Output Enable PAR : Parity PAR3-PAR0 : Bus Party PAR64 : Parity 64 bits PCBE7_B-PCBE0_B: Bus Command and Byte Enables PCI_MODE : PCI Mode PERR_B : Parity Error PHCE_B : PHY Chip Enable PHINT_B : PHY Interrupt PHOE_B : PHY Output Enable PHRST_B : PHY Reset PHR/W_B : PHY Read/Write PHYALM : Physical Alarm RCLK : Receive Clock RCIC : Receive Clock Input Complement RCIT : Receive Clock Input True RDIC : Receive Data Input Complement RDIT : Receive Data Input True PDY_B : Target Ready REFCLK : Reference Clock RENBL_B : Receive Enable REQ64_B : Request 64-bit Transfer REQ_B : Request RGND : Ground for Receive PLL Part ROMA15-ROMA0: Expansion ROM Address ROMCS_B : Expansion ROM Chip Select ROMD7-ROMD0 : Expansion ROM Input Data ROMOE_B : Expansion ROM Output Enable RSOC : Receive Start Cell RST_B : Reset RVDD3 : +3.3 V Power Supply for Receive PLL Part Rx7-Rx0 : Receive Data Bus SCLK : SAR System Clock SD : Signal Detect SEL_B : Slave Select SERR_B : System Error SIZE2-SIZE0 : Burst Size SR/W_B : Slave Read /Write STOP_B : Stop TCLK : Transmit Clock TDOC : Transmit Data Output Complement TDOT : Transmit Data Output True TENBL_B : Transmit Enable TEST : Test Mode Pin TFKC : Transmit Reference Clock Complement TFKT : Transmit Reference Clock True TRDY_B : Target Ready TSOC : Transmit Start of Cell Tx7-Tx0 : Transmit Data Bus VDD3 : +3.3 V Power Supply for Digital Part VDD5 : +5 V Power Supply for Digital Part Data Sheet S12689EJ2V0DS00 5 5 Page µPD98405 1.1.2 PHY device control interface (external PHY mode, PHM of GMR register = 1) Pin Name PHR/W_B (shared with PHYALM) Pin No. 266 PHOE_B 265 PHCE_B (shared with SD) PHINT_B (shared with REFCLK) 267 268 PHRST_B 264 I/O I/O Level Function O TTL PHY read/write. The µPD98405 indicates the PHY layer device control direction by using this pin. 1: Read 0: Write O TTL PHY layer output enable. The µPD98405 enables output by the PHY layer device by making this signal low. O TTL PHY layer chip enable. The µPD98405 makes this signal low when it accesses the PHY layer device. I TTL PHY layer interrupt. This pin inputs an interrupt signal to the µPD98405 from the PHY layer device. The PHY layer device informs the µPD98405 that it has an interrupt source by inputting a low level to this pin. Pull up this pin when it is not used. O TTL PHY layer reset. This signal is used to reset the PHY layer device. The µPD98405 keeps this pin low for the duration of 17 clock cycles when a low level is input to the RST_B pin or when software reset is executed. Caution The PHCE_B/SD pins are multiplexed pins and their functions differ depending on whether the internal PHY mode or external PHY mode is selected (by using the PHM bit of the GMR register). Because the PHCE_B/SD pins change the mode between input and output depending on the selected mode, be sure to correctly set the PHM bit of the GMR register. Data Sheet S12689EJ2V0DS00 11 11 Page

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