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PDF UPD98404GJ-KEU Data sheet ( Hoja de datos )
| Número de pieza | UPD98404GJ-KEU | |
| Descripción | ADVANCED ATM SONET FRAMER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98404
ADVANCED ATM SONET FRAMER
DESCRIPTION
The µPD98404 NEASCOT-P30TM is an LSI for ATM applications, which can be used in ATM adapter boards for
connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI
provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the
ATM Forum’s UNI3.1 recommendations.
This product’s main functions include transmission functions such as mapping of ATM cells sent from the ATM
layer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media
Dependent) sub-layer in the physical layer. Its reception functions include separation of the overhead from the ATM
cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer. In addition,
this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and
a clock synthesis function that generates a clock for transmissions.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD98404 User’s Manual: S11821E
FEATURES
• On-chip clock recovery/clock synthesis functions
• Provides TC sub-layer function for the ATM protocol’s physical layer
• Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1
• Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)
Supports three UTOPIA interfaces:
• Single PHY octet-level handshaking
• Single PHY cell-level handshaking
• Multi PHY mode
• Selectable to drop/bypass unassigned cells
• On-chip internal loopback functions for PMD layer loopback and ATM layer loopback
• Supports two PMD interfaces: serial and parallel
• 155.52 Mbps serial interface
• 19.44 MHz parallel interface
• Provides registers for writing/reading overhead information
SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte
LOH (line overhead) :K1 byte, K2 byte
POH (path overhead) :F2 byte, C2 byte, H4 byte
• Provides pseudo error frame transmit function for various errors
• Supports JTAG boundary scan test function (IEEE 1149.1)
• CMOS technology
• +3.3 V single power supply
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S11822EJ4V0DS00 (4th edition)
Date Published May 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997, 1999
1 page  
PIN CONFIGURATION
PMD interface
Test interface
RDIT, RDIC
RCIT, RCIC
TDOT, TDOC
TCOT, TCOC
TFKT, TFKC
Serial
AIN1
REFCLK
PSEL0, PSEL1
2
RPD0 - RPD7
8
RPC
TPD0 - TPD7 Parallel
8
TPC
TFC
PMDALM
PHYALM0 - PHYALM2
3
RxFP
TxFP
TFSS
RCL
TCL
Power
supply, GND
VDD, VDD-TPE, VDD-RPE
VDD-SP, VDD-CS, VDD-CR
GND, GND-TPE, GND-RPE
GND-SP, GND-CS, GND-CR
µPD98404
RDO0 - RDO7
RCLK
RSOC
RENBL_B
EMPTY_B/RCLAV
RADD0-RADD4
TDI0 - TDI7
TCLK
TSOC
TENBL_B
FULL_B/TCLAV
TADD0 - TADD4
UMPSEL
8
5 ATM
layer interface
8
5
MSEL
MADD0 - MADD6
MD0 - MD7
CS_B
DS_B/RD_B
R/W_B/WR_B
ACK_B/RDY_B
PHINT_B
RESET_B
7
8
Management
interface
JTAG boundary scan interface
Remark Active low pins are indicated with the suffix “_B” in this document.
Data Sheet S11822EJ4V0DS00
5
5 Page 
µPD98404
Pin name Pin No.
TxFP
14
I/O level
TTL*
TFSS 13 TTL*
RCL
75 TTL*
TCL 15 TTL*
(3/3)
I/O Function
O Frame pulse signal output for the transmit side (8 kHz). This pin
outputs a pulse signal at one-clock intervals in sync with the TCL
clock.
I Transmit frame output disable signal input. When the signal is high,
the transmit frame output stops. When the signal is low, transmission
starts from the beginning of a frame. The µPD98404 samples this
signal at the rising edge of the TCL clock. The transmit frame output
is resumed at the ninth rising edge of the TCL clock after the rising
edge at which the high level of this signal was last detected.
O Internal system clock output for the receive side (19.44 MHz). This
pin outputs the receive clock divided by 8. The source receive clock
depends on the selected mode, which is either the clock generated by
the internal clock recovery PLL or the clock supplied from the
RCIT/RCIC and RFC pins. Clock output from this pin is stopped while
the device is being reset.
O Internal system clock output of the transmit side (19.44 MHz).
This pin outputs the transmit clock divided by 8. The source transmit
clock depends on the selected mode, which is either the clock
generated by the internal synthesizer or the clock supplied from the
TCIT/TCIC and TFC pins. Clock output from this pin is stopped while
the device is being reset.
1.2 ATM layer interface
Pin name Pin No. I/O level
RDO0-
RDO7
130-137
TTL*
RCLK 128 TTL*
RSOC
126
TTL*
RENBL_B 127
TTL*
(1/2)
I/O Function
O Receive data output.
(2 or 3- These pins form an 8-bit data bus that outputs receive data to an ATM
state) layer device. The data is output in sync with the rising edge of the
RCLK clock. These pins operate in two or three states, depending on
the UTOPIA interface mode.
I Receive clock input. This pin supplies a clock of up to 40 MHz for
receive data transfer.
O Receive cell start position signal output.
(2 or 3- This pin outputs a signal indicating the position of the first byte of a
state) receive cell. This pin operates in two or three states, depending on
the UTOPIA interface mode.
I Receive enable signal input.
This pin inputs a signal indicating that the ATM layer is ready to
receive data.
Data Sheet S11822EJ4V0DS00
11
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