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PDF UPD784218YGC Data sheet ( Hoja de datos )
| Número de pieza | UPD784218YGC | |
| Descripción | 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784218, 784218Y
16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD784218 is a member of the µPD784218 Subseries of the 78K/IV Series. In addition to a high-speed and
high-performance CPU, the µPD784218 incorporates a variety of peripheral hardware such as ROM, RAM, I/O ports,
8-bit resolution A/D and D/A converters, timers, serial interfaces, real-time output ports, and an interrupt function.
The µPD784218YNote is the µPD784218 Subseries with a multi-master supporting I2C bus interface added.
Flash memory versions, the µPD78F4218 and 78F4218Y, which can operate in the same voltage range as the
mask ROM versions, and various development tools are also available.
Note Under development
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD784218, 784218Y Subseries User’s Manual Hardware: U12970E
78K/IV Series User’s Manual Instructions:
U10905E
FEATURES
• On-chip ROM correction function
• Inherits peripheral functions of µPD78078Y Subseries
• Minimum instruction execution time
160 ns
(@ fXX = 12.5 MHz operation with main system clock)
61 µs
(@ fXT = 32.768 kHz operation with subsystem clock)
• Internal high-capacity memory
· ROM: 256 KB
· RAM: 12,800 bytes
• I/O ports: 86
• Timer/counters: 16-bit timer/event counter × 1 unit
8-bit timer/event counter × 6 units
• Serial interfaces: 3 channels
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, multi-master supporting I2C
busNote): 1 channel
• Standby function
HALT/STOP/IDLE mode
In power-saving mode: HALT/IDLE mode (with
subsystem clock)
• Clock division function
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Clock output function
Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24,
fXX/25, fXX/26, fXX/27, fXT
• Buzzer output function
Selectable from fXX/210, fXX/211, fXX/212, fXX/213
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Supply voltage: VDD = 2.2 to 5.5 V
Note µPD784218Y only
Unless otherwise specified, references in this document to the µPD784218 refer to the µPD784218 and
the µPD784218Y.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12304EJ2V0DS00 (2nd edition)
Date Published March 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997, 2000
1 page  
µPD784218, 784218Y
OVERVIEW OF FUNCTIONS (2/2)
Item
Clock output
Buzzer output
Part Number
µPD784218, µPD784218YNote
Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
Selectable from fXX/210, fXX/211, fXX/212, fXX/213
Watch timer
1 channel
Watchdog timer
1 channel
Standby
• HALT/STOP/IDLE modes
• In low-power consumption mode (with subsystem clock): HALT/IDLE mode
Interrupts
Hardware sources 29 (internal: 20, external: 9)
Software sources BRK instruction, BRKCS instruction, operand error
Non-maskable
Internal: 1, external: 1
Maskable
Internal: 19, external: 8
• 4 programmable priority levels
• 3 service modes: vectored interrupt/macro service/context switching
Supply voltage
VDD = 2.2 to 5.5 V
Package
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Note Under development
Data Sheet U12304EJ2V0DS00
5
5 Page 
• 100-pin plastic QFP (14 × 20 mm)
µPD784218GF-×××-3BA, 784218YGF-×××-3BANote 5
µPD784218, 784218Y
P60/A16
P61/A17
P62/A18
P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
VDD
P100/TI5/TO5
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/TI00
P36/TI01
P37/EXA
TESTNote 1
P90
P91
P92
P93
P94
P95
P120/RTP0
P121/RTP1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P84/A4
P83/A3
P82/A2
P81/A1
P80/A0
P27/SCK0/SCL0Note 4
P26/SO0
P25/SI0/SDA0Note 4
P24/BUZ
P23/PCL
P22/ASCK1/SCK1
P21/TxD1/SO1
P20/RxD1/SI1
P72/ASCK2/SCK2
P71/TxD2/SO2
P70/RxD2/SI2
AVREF1
P131/ANO1
P130/ANO0
AVSSNote 3
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVREF0
AVDDNote 2
Notes 1. Connect the TEST pin directly to VSS or pull down. For the pull-down connection, use of a resistor whose
resistance is between 470 Ω and 10 kΩ is recommended.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
4. The SCL0 and SDA0 pins are incorporated only in the µPD784218Y.
5. Under development
Data Sheet U12304EJ2V0DS00
11
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