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PDF UPD77019-013 Data sheet ( Hoja de datos )
| Número de pieza | UPD77019-013 | |
| Descripción | 16 bits/ Fixed-point Digital Signal Processor | |
| Fabricantes | NEC | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77019-013
16 bits, Fixed-point Digital Signal Processor
The µPD77019-013 is a masked 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal
processing with its demand for high speed and precision.
The µPD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask
code ordering process. Also the µPD77019-013 can operate as simplified evaluate chip for as the µPD7701x family.
About mask ROM and mask option, there are following differences between the µPD77019-013 and µPD77019.
PLL clock multiple rate
Crystal resonator
connection
Clock Input pin
Clock output pin
Internal mask ROM
Self boot
Fixed to 4
µPD77019-013
Disable (PLL clock multiple rate is fixed to 4.)
External clock is connected to the X1 pin.
Leave the X2 pin open.
Output internal system clock.
Not available (already masked by the void
code)
Enable to boot from external data area (Boot
information data is masked.) Refer to 2.6
Boot Function.
µPD77019
Variable multiple rate (1, 2, 3, 4, 8) by mask
option
Enable (PLL clock multiple rate is set to 1 by
mask option.)
External clock is connected to the X1 pin.
Crystal is connected between the X1 pin and
X2 pin.
Low level fixed, or internal system clock
output is selectable by mask option.
Coding user program or data when ordering
mask ROM.
Enable to boot from internal data ROM or
external data area.
ORDERING INFORMATION
Part Number
µPD77019GC-013-9EU
Package
100-pin plastic TQFP (FINE PITCH) (14 × 14 mm)
The µPD7701x family consists of the µPD77016, 77015, 77017, 77018, 77018A and µPD77019.
The information in this document is subject to change without notice.
Document No. U13053EJ1V0DS00 (1st edition)
Date Published March 1998 N CP(K)
Printed in Japan
©
1998
1 page  
Functional Differences among the µPD7701× Family
Item
Internal instruction RAM
Internal instruction ROM
External instruction memory
Data RAM (X/Y memory)
Data ROM (X/Y memory)
External data memory
Instruction cycle
(Maximum operation speed)
External clock
(at maximum operation speed)
µPD77016
1.5K words
None
48K words
2K words each
None
48K words each
66 MHz
µPD77015
4K words
1K words each
2K words each
µPD77017
µPD77018
µPD77018A
µPD77019
µPD77019-013
256 words
4K words
12K words
24K words
None
None
2K words each
3K words each
4K words each
12K words each
None
16K words each
30 ns (33 MHz)
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
16.6 ns (60 MHz)
60/30/20/15/7.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
15 MHz
Multiple rate is
fixed to 4.
Crystal
(at maximum operation speed)
–
Instruction
–
Serial interface (2 Channels)
Channel 1 has the
same functions
as channel 2.
Power supply
5V
Package
160-pin plastic QFP
33 MHz
60 MHz
STOP instruction is added.
Channel 1 has the same functions as that of the µPD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
100-pin plastic TQFP
3V
100-pin plastic TQFP
116-pin plastic BGA
–
100-pin plastic TQFP
5 Page 
µPD77019-013
• External data memory interface
Symbol
Pin No.
X/Y 7
DA13 - DA0
8, 9, 12 -19, 22 - 25
D15 - D0
MRD
MWR
WAIT
26 -29, 32 - 35, 38 - 41,
44 - 47
98
95
100
HOLDRQ
BSTB
HOLDAK
93
99
94
I/O Function
O Memory select signal output
(3S) • 0: X memory is used.
• 1: Y memory is used.
O Address bus to external data memory
(3S) • External data memory is accessed.
• During the external memory is not accessed, these pins
keep the previous level.
These pins are set to low level; 0x0000, by reset.
They continue outputting low level until the first external
memory access.
I/O 16 bits data bus to external data memory
(3S) • External data memory is accessed.
O Read output
(3S) • Reads external memory
O Write output
(3S) • Writes external memory
I Wait signal input
• Wait cycle is input when external memory is read.
1: No wait
0: Wait
I Hold request signal input
• Input low level when external data memory bus is
expected to use.
O Bus strobe signal output
• Outputs low level while the µPD77019-013 is occupying
external memory bus.
O Hold acknowledge signal output
• Outputs low level when the µPD77019-013 permits external
device to use external data memory bus.
Remark The state of the pins added 3S becomes high impedance when the external memory is not accessed
and when bus release signal (HOLDAK = 0) is output.
Preliminary Data Sheet
11
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