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PDF UPD75P3216GT Data sheet ( Hoja de datos )
| Número de pieza | UPD75P3216GT | |
| Descripción | 4-BIT SINGLE-CHIP MICROCONTROLLER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P3216
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P3216 replaces the µPD753208’s internal mask ROM with a one-time PROM, and features expanded
ROM capacity.
Because the µPD75P3216 supports programming by users, it is suitable for use in prototype testing for system
development using the µPD753204, 753206, or 753208, and for use in small-lot production.
The functions are explained in detail in the following user’s manual. Be sure to read this manual when
designing your system.
µPD753208 User’s Manual: U10158E
FEATURES
• Compatible with µPD753208
• Memory capacity:
• PROM : 16384 × 8 bits
• RAM : 512 × 4 bits
• Can operate in same power supply voltage range as the mask version µPD753208
• VDD = 1.8 to 5.5 V
• LCD controller/driver
ORDERING INFORMATION
Part Number
µPD75P3216GT
Package
48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
Caution Mask-option pull-up resistors are not provided in this device.
The information in this document is subject to change without notice.
Document No. U10241EJ1V0DS00 (1st edition)
Date Published January 1997 N
Printed in Japan
The mark shows major revised points.
'©
19957
1 page  
2. BLOCK DIAGRAM
µPD75P3216
BUZ/P23
TI0/P13
PTO0/P20
WATCH
TIMER
INTW fLCD
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
8-BIT
TIMER/EVENT
COUNTER #0
INTT0 TOUT
PTO1/P21
TOUT
PTO2/
PCL/P22
INTT1
8-BIT
TIMER CASCADED
COUNTER #1 16-BIT
8-BIT
TIMER
TIMER
COUNTER
COUNTER #2
INTT2
SI/SB1/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
INTCSI TOUT
INT0/P10
INT4/P00
KR0/P60-
KR3/P63 4
INTERRUPT
CONTROL
BIT SEQ.
BUFFER (16)
PORT0 4 P00-P03
PROGRAM
COUNTER
SP (8)
CY
ALU SBS
BANK
GENERAL
REG.
PORT1 2 P10, P13
PORT2 4 P20-P23
PORT3
4
P30/MD0-
P33/MD3
PORT5
4
P50/D4-
P53/D7
PORT6
4
P60/D0-
P63/D3
PROM
PROGRAM
MEMORY
16384 × 8 BITS
DECODE
AND
CONTROL
DATA
MEMORY
(RAM)
512 × 4 BITS
PORT8 4 P80-P83
PORT9 4 P90-P93
4 S12-S15
fx/2 N
CPU CLOCK Φ
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
SYSTEM
CLOCK
GENERATOR
STANDBY
CONTROL
4
LCD
CONTROLLER/ 4
DRIVER
fLCD
4
PCL/PTO2/P22
X1 X2
Vpp VDD VSS RESET
S16/P93-
S19/P90
S20/P83-
S23/P80
COM0-COM3
VLC0
VLC1
VLC2
BIAS
LCDCL/P30
SYNC/P31
5
5 Page 
µPD75P3216
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the µPD75P3216 enables the program memory to be switched
between Mk I mode and Mk II mode. This function is applicable when using the µPD75P3216 to evaluate the µPD753204,
753206, or 753208.
When the SBS bit 3 is set to 1: sets Mk I mode (supports Mk I mode for µPD753204, 753206, and 753208)
When the SBS bit 3 is set to 0: sets Mk II mode (supports Mk II mode for µPD753204, 753206, and 753208)
4.1 Difference between Mk I Mode and Mk II Mode
Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3216.
Table 4-1. Difference between Mk I Mode and Mk II Mode
Item Mk I Mode
Program counter
PC13-0
Program memory (bytes)
16384
Data memory (bits)
512 × 4
Stack
Stack bank
Selectable via memory banks 0, 1
No. of stack bytes
2 bytes
Instruction BRA !addr1 instruction None
CALLA !addr1 instruction
Instruction CALL !addr instruction
execution time CALLF !faddr instruction
3 machine cycles
2 machine cycles
Supported mask ROMs
When set to Mk I mode:
µPD753204, 753206, and 753208
Mk II Mode
3 bytes
Provided
4 machine cycles
3 machine cycles
When set to Mk II mode:
µPD753204, 753206, and 753208
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore,
when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine
cycle. Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
11
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