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Número de pieza | UPD75517 | |
Descripción | 4 BIT SINGLE-CHIP MICROCOMPUTER | |
Fabricantes | NEC | |
Logotipo | ||
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No Preview Available ! ELECTRON DEVICE
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75517(A)
4 BIT SINGLE-CHIP MICROCOMPUTER
The µPD75517(A) is a 75X series four-bit single-chip microcomputer which enables data processing
equivalent to that performed by an eight-bit microcomputer. It is a high-performance product, whose
minimum instruction execution time is 0.67 µs, shorter than 0.95 µs for the conventional µPD75516. The ROM
and RAM capacities are also larger, and the throughput of the 75X series is further increased. The µPD75517(A)
is suited to controllers of electric parts of automobiles.
FEATURES
• Higher reliable than the µPD75517
• Capacities of program memory, ROM: 24448 × 8 bits
• Capacity of data memory, RAM: 1024 × 4 bits
• Function for specifying the instruction execution time (useful for high-speed operation and saving power)
• 0.67 µs/1.33 µs/2.67 µs/10.7 µs (when the main system clock operates at 6.0 MHz)
• 0.95 µs/1.91 µs/3.82 µs/15.3 µs (when the main system clock operates at 4.19 MHz)
• 122 µs (when the subsystem clock operates at 32.768 kHz)
• Built-in A/D converter operable on low voltage
• 8-bit resolution × 8 channels (Successive approximation system)
• VDD = 2.7 to 6.0 V
• Many I/O lines: 64
• Enhanced timer function: 4 channels
• Built-in 8-bit serial interface: Two channels
• Built-in NEC serial bus interface (SBI)
• Clock operable with ultra-low power consumption (when 5-µA TYP. operates on 3 V.)
• Product with a built-in PROM available: µPD75P518
APPLICATIONS
Controller of electric parts of automobiles
ORDERING INFORMATION
Part number
uPD75517GF(A)-×××-3B9
Package
80-pin plastic QFP (14 mm × 20 mm)
Quality grade
Special
Remark ×××: Code number
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Document No.
(O. D. No.
Date Published
Printed in Japan
IC-3183
IC-8683
November 1992 P
The information in this document is subject to change without notice.
NEC CORPORATION1992
1 page CONTENTS
µPD75517(A)
1. PIN FUNCTIONS ........................................................................................................................
1.1 PORT PINS ......................................................................................................................................
1.2 NON-PORT PINS ............................................................................................................................
1.3 PIN INPUT/OUTPUT CIRCUITS ....................................................................................................
1.4 CONNECTION OF UNUSED PINS ................................................................................................
1.5 SELECTION OF A MASK OPTION ................................................................................................
7
7
9
10
13
14
2. ARCHITECTURE AND MEMORY MAP OF THE µPD75517(A) .............................................. 15
2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................ 15
2.2 GENERAL REGISTER BANK CONFIGURATION .......................................................................... 19
2.3 MEMORY-MAPPED I/O ................................................................................................................. 22
3. INTERNAL CPU FUNCTIONS .................................................................................................... 27
3.1 PROGRAM COUNTER (PC) ........................................................................................................... 27
3.2 PROGRAM MEMORY (ROM) ........................................................................................................ 27
3.3 DATA MEMORY (RAM) ................................................................................................................. 29
3.4 GENERAL REGISTERS ................................................................................................................... 31
3.5 ACCUMULATORS .......................................................................................................................... 32
3.6 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ..................................... 32
3.7 PROGRAM STATUS WORD (PSW) .............................................................................................. 35
3.8 BANK SELECT REGISTER (BS) ..................................................................................................... 38
4. PERIPHERAL HARDWARE FUNCTIONS .................................................................................. 39
4.1 DIGITAL I/O PORTS ....................................................................................................................... 39
4.2 CLOCK GENERATOR ...................................................................................................................... 51
4.3 CLOCK OUTPUT CIRCUIT ............................................................................................................. 60
4.4 BASIC INTERVAL TIMER ............................................................................................................... 63
4.5 CLOCK TIMER ................................................................................................................................. 67
4.6 TIMER/EVENT COUNTER ............................................................................................................. 69
4.7 TIMER/PULSE GENERATOR ......................................................................................................... 75
4.8 SERIAL INTERFACE (CHANNEL 0) ............................................................................................... 83
4.8.1 Serial Interface (Channel 0) Functions ........................................................................ 84
4.8.2 Configuration of Serial Interface (Channel 0) ............................................................ 84
4.8.3 Register Functions ......................................................................................................... 86
4.8.4 Signals ............................................................................................................................. 94
4.8.5 Serial Interface (Channel 0) Operation ....................................................................... 100
4.8.6 Transfer Start in Each Mode ........................................................................................ 110
4.8.7 Manipulation of SCK0 Pin Output ............................................................................... 111
5
5 Page µPD75517(A)
Fig. 1-1 Pin Input/Output Circuits (2/3)
Type E - C
P.U.R.
enable
Data
Output
disable
Type F
Data
Output
disable
Type F - B
Type D
VDD
P.U.R.
P-ch
IN/OUT
Type A
P.U.R.: Pull-Up Resistor
Output
disable
(P-ch)
Data
Output
disable
Output
disable
(N-ch)
Type F - C
Type D
IN/OUT
Type B
P.U.R.
enable
Data
Output
disable
P.U.R.
enable
VDD
P.U.R.
P-ch
VDD
P-ch
IN/OUT
N-ch
Type B
P.U.R.: Pull-Up Resistor
VDD
P.U.R.
P-ch
Type D
IN/OUT
I/O circuit consisting of a push-pull output of type D
and a Schmitt-triggered input of type B
Type F - A
P.U.R.
enable
VDD
P.U.R.
P-ch
Data
Output
disable
Type D
IN/OUT
Type M
Data
Output
disable
Type B
P.U.R.: Pull-Up Resistor
VDD
P.U.R.
(Mask option)
IN/OUT
N-ch
(Can sustain
+9 V)
Type B
P.U.R.: Pull-Up Resistor
Middle-voltage input buffer
(Can sustain + 10 V)
P.U.R.: Pull-Up Resistor
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet UPD75517.PDF ] |
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