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PDF UPD754264 Data sheet ( Hoja de datos )
| Número de pieza | UPD754264 | |
| Descripción | 4-BIT SINGLE-CHIP MICROCONTROLLERS | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD754264
4-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD754264 is a 4-bit single-chip microcontroller which incorporates the EEPROMTM for key-less entry
application.
It incorporates a 32 × 8-bit EEPROM, a CPU performing operation, a 4-Kbyte mask ROM to store software,
a 128 × 4-bit RAM to store the operation data, an 8-bit resolution A/D converter, and a carrier generator which
easily outputs waveforms for infrared remote controller.
The details of functions are described in the following user’s manual. Be sure to read it before designing.
µPD754264 User’s Manual: U12287E
FEATURES
• On-chip EEPROM: 32 × 8 bits (mapped to the data memory)
• On-chip key return reset function for key-less entry
• On-chip low-voltage A/D converter (AVREF = 1.8 to 6.0 V), 8-bit resolution × 2 channels
• Low-voltage operation: VDD = 1.8 to 6.0 V
• Timer function (4 channels)
• Basic interval timer/watchdog timer : 1 channel
• 8-bit timer counter
: 3 channels
• On-chip memory
• Program memory (ROM)
4096 × 8 bits
• Data memory (static RAM)
128 × 4 bits
• Instruction execution time variable function suited for high-speed operation and power saving.
0.95, 1.91, 3.81, 15.3 µs (@ fX = 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7 µs (@ fX = 6.0-MHz operation)
APPLICATIONS
Automotive appliances such as key-less entry, compact data carrier, etc.
ORDERING INFORMATION
Part Number
µPD754264GS-×××-BA5
Package
20-pin plastic SOP (300 mil, 1.27-mm pitch)
Remark ××× indicates ROM code suffix.
Document No. U12487EJ1V1DS00
Date Published January 1999 N CP(K)
Printed in Japan
The information in this document is subject to change without notice.
The mark shows major revised points.
©
1997
1 page  
µPD754264
1. PIN CONFIGURATION (TOP VIEW)
• 20-pin Plastic SOP (300 mil, 1.27-mm pitch)
µPD754264GS-×××-BA5
RESET
X1
X2
VSS
IC
VDD
P60/AVREF
P61/INT0
P62/AN0
P63/AN1
1
2
3
4
5
6
7
8
9
10
20 KRREN
19 P80
18 P30/PTO0
17 P31/PTO1
16 P32/PTO2
15 P33
14 P70/KR4
13 P71/KR5
12 P72/KR6
11 P73/KR7
IC: Internally Connected (Connect to VDD directly)
Pin Identification
AN0, AN1
AVREF
IC
INT0
KR4 to KR7
KRREN
P30 to P33
P60 to P63
: Analog input 0,1
: Analog reference
: Internally connected
: External vectored interrupt 0
: Key returns 4 to 7
: Key return reset enable
: Port 3
: Port 6
P70 to P73
: Port 7
P80 : Port 8
PTO0 to PTO2 : Programmable timer outputs 0 to 2
RESET
: Reset
VDD : Positive power supply
VSS : Ground
X1 and X2
: System clock (crystal/ceramic)
5
5 Page 
µPD754264
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference between Mk I and Mk II Modes
The µPD754264 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by the bit 3 of the Stack Bank Select register (SBS).
• Mk I mode:
• Mk II mode:
Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
Incompatible with 75X Series. Can be used in all the 75XL CPU’s including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Number of stack bytes
for subroutine instructions
BRA !addr1 instruction
CALLA !addr1 instruction
CALL !addr instruction
CALLF !faddr instruction
2 bytes
Mk I Mode
Not available
3 machine cycles
2 machine cycles
Mk II Mode
3 bytes
Available
4 machine cycles
3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.
Therefore, this mode is effective for enhancing software compatibility with products that have a
program area of more than 16 Kbytes.
With regard to the number of stack bytes during execution of subroutine call instructions, the usable
area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes
longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and
processing performance than on software compatibility, the Mk I mode should be used.
11
11 Page | ||
| Páginas | Total 68 Páginas | |
| PDF Descargar | [ Datasheet UPD754264.PDF ] | |
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