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PDF UPD75218 Data sheet ( Hoja de datos )
| Número de pieza | UPD75218 | |
| Descripción | 4-BIT SINGLE-CHIP MICROCOMPUTER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75218
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75218 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, ROM, RAM,
I/O ports, an FIP controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM pulses,
a serial interface and a vectored interrupt function integrated on a single chip.
It is most suitable for applications which use fluorescent display tubes as display devices and require the timer/
watch function and high-speed interrupt servicing, such as VCR, CD and ECR. It can help to provide the unit with
many functions and to decrease performance costs.
The µPD75218 has larger ROM and RAM capacity than its predecessor, µPD75217. So several codes required
before have been reduced to only one code in the µPD75218 specifications.
The one-time PROM product, µPD75P218 and various development tools (IE-75001-R, assembler, etc.) are
available for system development evaluation or small production.
The following manual provides detailed description of the functions of the µPD75218. Be sure to read this manual
when you design an application system.
µPD75218 User’s Manual: IEU-692
FEATURES
• On-chip large-capacity ROM and RAM
• Program memory (ROM) : 32K × 8 bits
• Data memory (RAM) : 1K × 4 bits
• Architecture equal to that of an 8-bit microcomputer
• High-speed operation: Minimum instruction execution time : 0.67 µs (when the microcomputer operates at
6.0 MHz)
• Instruction execution time variable function realizing a wide range of operating voltages
• On-chip programmable fluorescent indication panel (FIP) controller/driver
• Timer function : 4 ch
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner
• Buzzer output capability
• Interrupt function with importance attached to applications
• For power-off detection
• For reception of remote-controller signal
• Product with an on-chip PROM : µPD75P218 (on-chip EPROM : WQFN package)
Document No. IC-3035
(O. D. No. IP-8484)
Date Published November 1993 P
Printed in Japan
The information in this document is subject to change without notice.
Major changes in this version are indicated by stars (5) in the margins.
© NEC Corporation 1993
1 page  
1. PIN CONFIGURATION (TOP VIEW)
S3
S2
S1
S0
P00/INT4
P01/SCK
P02/SO
P03/SI
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20
P21
P22
P23/BUZ
P30
P31
P32
P33
P60
P61
P62
P63
P40
P41
P42
P43
PPO
X1
X2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64 VDD
63 S4
62 S5
61 S6
60 S7
59 S8
58 S9
57 VPRE
56 VLOAD
55 T15/S10
54 T14/S11
53 T13/S12/PH0
52 T12/S13/PH1
51 T11/S14/PH2
50 T10/S15/PH3
49 T9
48 T8
47 T7
46 T6
45 T5
44 T4
43 T3
42 T2
41 T1
40 T0
39 RESET
38 P53
37 P52
36 P51
35 P50
34 XT2
33 XT1
µPD75218
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P41 52
32 P01/SCK
P42 53
31 P00/INT4
P43 54
30 S0
PPO
55
29 S1
X1 56
28 S2
X2 57
VSS 58
µPD75218GF-× × ×-3BE
27 S3
26 VDD
XT1 59
25 S4
XT2 60
24 S5
P50 61
23 S6
P51 62
22 S7
P52 63
21 S8
P53 64
20 S9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
5
5 Page 
µPD75218
3.5 NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN
P00/INT4 and RESET pins have the function (especially for IC test) to test µPD75218 internal operations in addition
to the functions described in sections 3.1 and 3.2.
The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is
applied in normal operation, the test mode may be set thereby adversely affecting normal operation.
Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,
if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4
and RESET pins causing errors.
Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure
against noise using the following external components.
• Connecting a diode between the pins and VDD
VDD
VDD
P00/INT4, RESET
• Connecting a capacitor between the pins and VDD
VDD
VDD
P00/INT4, RESET
3.6 NOTES ON USE OF THE XT1, XT2 AND P50 PIN
When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source
clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched
between high and low the minimum number of times (once/second or less).
If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because
of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch
becomes fast).
If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the
P50 pin as shown below.
µ PD75218
P50
XT1 XT2
32.768 kHz
0.0068 µ F
11
11 Page | ||
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