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PDF UPD75066GB Data sheet ( Hoja de datos )

Número de pieza UPD75066GB
Descripción 4-BIT SINGLE-CHIP MICROCOMPUTER
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75064, 75066, 75068,
75064(A), 75066(A), 75068(A)
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75068 is a member of the 75X series of 4-bit single-chip microcomputers.
The minimum instruction execution time of the µPD75068's CPU is 0.95 µs. In addition to this high-speed
capability, the chip contains an A /D converter and furnishes high-performance functions such as the serial
bus interface (SBI) function compliant with the NEC standard format, providing powerful features and high
cost performance. The µPD75068(A) is a high-reliability version of the µPD75068.
NEC also provides PROM versions suitable for small-scale production or evaluation samples in system
development. The µPD75P068 is the PROM version for the µPD75064, 75066, 75068, and the µPD75P068(A)
is that for the µPD75064(A), 75066(A), 75068(A).
The detailed function descriptions are described in the document below. Please make sure to read this
document before starting design.
µPD75068 User's Manual: IEU-1366
FEATURES
Variable instruction execution time advantageous to high-speed operation and power-saving:
• 0.95 µs, 1.91 µs, or 15.3 µs (at 4.19 MHz with the main system clock selected)
• 122 µs (at 32.768 kHz with the subsystem clock selected)
A /D converter (8-bit resolution, successive approximation): 8 channels
• Capable of low-voltage operation: VDD = 2.7 to 6.0 V
Timer function: 3 channels
On-chip NEC standard serial bus interface (SBI)
Very low-power watch operation enabled (5 µA TYP. at 3 V)
Pull-up resistor option allowed for 27 I/O lines
The µPD75P068 and 75P068(A) (PROM versions) available: Capable of low-voltage operation (VDD = 2.7 to
6.0 V)
APPLICATIONS
µPD75064, 75066, 75068
Home electronic appliances, air conditioners, cameras, and electronic measuring instruments
µPD75064(A), 75066(A), 75068(A)
Automotive electronics
5
The information in this document is subject to change without notice.
Document No. IC-3140B
( O.D. No. IC-8629B)
Date Published December 1994 P
Printed in Japan
The mark 5 shows revised points.
NEC CORPORATION 1993

1 page




UPD75066GB pdf
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
1. PIN CONFIGURATION (TOP VIEW)
• 42-pin plastic shrink DIP
XT1
XT2
RESET
X1
X2
P33
P32
P31
P30
AVSS
AN7/KR3/P63
AN6/KR2/P62
AN5/KR1/P61
AN4/KR0/P60
AN3/P113
AN2/P112
AN1/P111
AN0/P110
AVREF
IC
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VSS
41 P40
40 P41
39 P42
38 P43
37 P50
36 P51
35 P52
34 P53
33 P00/INT4
32 P01/SCK
31 P02/SO/SB0
30 P03/SI/SB1
29 P10/INT0
28 P11/INT1
27 P12/INT2
26 P13/TI0
25 P20/PTO0
24 P21
23 P22/PCL
22 P23/BUZ
• 44-pin plastic QFP
INT2 /P12
INT1/P11
INT0/P10
SB1/SI/P03
SB0/SO/P02
SCK /P01
INT4/P00
P53
P52
P51
P50
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5 µ PD75064GB-×××-3B4
6 µ PD75066GB-×××-3B4
7 µ PD75068GB-×××-3B4
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
33
32
31
30
29
28
27
26
25
24
23
P112/AN2
P113/AN3
P60/KR0/AN4
P61/KR1/AN5
P62/KR2/AN6
P63/KR3/AN7
AVSS
P30
P31
P32
P33
IC : Internally Connected (This pin should be directly connected to VDD)
5

5 Page





UPD75066GB arduino
Type F-A
Data
Output
disable
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
P.U.R.
enable
Type D
Type B
VDD
P.U.R.
P-ch
IN/OUT
Type M-C
Data
Output
disable
P.U.R.
enable
(2/3)
VDD
P.U.R.
P-ch
IN/OUT
N-ch
P.U.R.: Pull-Up Resistor
P.U.R.: Pull-Up Resistor
Type F-B
Output
disable
(P)
Data
Output
disable
Output
disable
(N)
P.U.R.
enable
Type Y (For type Y-A , Y-D)
VDD
VDD
P-ch
N-ch
P.U.R.
P-ch
IN
VDD
IN/OUT
P-ch
N-ch
Sampl-
ing C
VDD
+
AVSS
Input
enable
AVSS
Reference voltage
(from voltage tap of
serial resistor string)
Type M
Data
Output
disable
P.U.R.: Pull-Up Resistor
VDD
P.U.R.
enable
(Mask option)
Type Y-A
IN/OUT
N-ch
(Can
withstand
+10 V)
IN
Type Y
IN instruction
Type A
Input buffer
Middle-voltage input buffer
(Can withstand +10 V)
P.U.R.: Pull-Up Resistor
11

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