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PDF UPD72870F1-FA2 Data sheet ( Hoja de datos )
| Número de pieza | UPD72870F1-FA2 | |
| Descripción | IEEE1394 1-CHIP OHCI HOST CONTROLLER | |
| Fabricantes | NEC | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72870,72871
IEEE1394 1-CHIP OHCI HOST CONTROLLER
The µPD72870, 72871 are the LSIs which integrated OHCI-Link and PHY function into a single chip.
The µPD72870, 72871 comply with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0 and work
up to 400 Mbps.
These make design so compact for PC and PC card application.
FEATURES
• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0
• Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)
3-port : µPD72870
1-port : µPD72871
• Compliant with protocol enhancement as defined in P1394a draft 2.0
• Modular 32-bit host interface compliant to PCI Specification release 2.1
• Support PCI-Bus Power Management Interface Specification release 1.0
• Modular 32-bit host interface compliant to Card Bus Specification
• Cycle Master and Isochronous Resource Manager capable
5 • Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048
bytes)
• 32-bit CRC generation and checking for receive/transmit packets
• 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
• 32-bit DMA channels for physical memory read/write
• Clock generation by 24.576 MHz X’tal
• Internal control and operational registers direct-mapped to PCI configuration space
• 2-wire Serial EEPROMTM interface supported
• Separate power supply Link and PHY
ORDERING INFORMATION
Part number
µPD72870GM-8ED
µPD72870F1-FA2
µPD72871GM-8ED
µPD72871 F1-FA2
Package
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
192-pin Plastic FBGA (14 x 14 mm)
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
192-pin Plastic FBGA (14 x 14 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13925EJ2V0DS00 (2nd edition)
Date Published September 1999 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
1999
1 page  
5 PIN CONFIGURATION
• 160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
µPD72870GM-8ED
Top View
L_VDD
CLKRUN
PME
INTA
PRST
PCLK
GNT
REQ
DGND
PCI_VDD
AD31
AD30
AD29
AD28
DGND
AD27
AD26
AD25
AD24
L_VDD
DGND
CBE3
IDSEL
AD23
AD22
AD21
AD20
DGND
AD19
AD18
PCI_VDD
AD17
AD16
DGND
CBE2
FRAME
IRDY
TRDY
DEVSEL
L_VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
µPD72870,72871
120 P_AVDD
119 AGND
118 XO
117 XI
116 P_AVDD
115 FIL0
114 FIL1
113 AGND
112 AGND
111 P_AVDD
110 P_RESETB
109 DGND
108 P_DVDD
107 P_AVDD
106 SUS_RESM
105 PORTDIS
104 DGND
103 P_DVDD
102 IC(L)
101 IC(L)
100 IC(H)
99 IC(H)
98 DGND
97 P_DVDD
96 CMC
95 PC2
94 PC1
93 PC0
92 IC(N)
91 IC(L)
90 DGND
89 IC(L)
88 IC(N)
87 IC(N)
86 IC(N)
85 DGND
84 IC(N)
83 IC(N)
82 IC(N)
81 L_VDD
Preliminary Data Sheet S13925EJ2V0DS00
5
5 Page 
µPD72870,72871
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................... 13
1.1 PCI/Cardbus Interface Signals: (52 pins)..................................................................................... 13
1.2 Cable Interface Signals: (15 pins) ................................................................................................ 14
1.3 PHY Signals: (9 pins)..................................................................................................................... 15
1.4 PHY Control Signals: (5 pins) ....................................................................................................... 15
1.5 PCI/Cardbus Select Signals: (2 pins) ........................................................................................... 16
1.6 Serial ROM Interface Signals: (3 pins) ......................................................................................... 16
1.7 Miscellaneous Signals: (1 pin)...................................................................................................... 16
1.8 IC: ( 21 pins) ................................................................................................................................... 17
1.9 VDD ................................................................................................................................................... 17
1.10 GND ............................................................................................................................................... 17
2. PHY REGISTERS .................................................................................................................................. 18
2.1 Complete Structure for PHY Registers ........................................................................................ 18
2.2 Port Status Page (Page 000) ......................................................................................................... 21
2.3 Vendor ID Page (Page 001) ........................................................................................................... 22
3. CONFIGURATION REGISTERS........................................................................................................... 23
3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) ........................................................ 23
3.1.1 Offset_00 Vendor ID Register............................................................................................................ 24
3.1.2 Offset_02 DeviceID Register ............................................................................................................. 24
3.1.3 Offset_04 Command Register ........................................................................................................... 24
3.1.4 Offset_06 Status Register.................................................................................................................. 25
3.1.5 Offset_08 Revision ID Register.......................................................................................................... 26
3.1.6 Offset_09 Class Code Register ......................................................................................................... 26
3.1.7 Offset_0C Cache Line Size Register ................................................................................................. 26
3.1.8 Offset_0D Latency Timer Register..................................................................................................... 26
3.1.9 Offset_0E Header Type Register....................................................................................................... 26
3.1.10 Offset_0F BIST Register................................................................................................................... 26
3.1.11 Offset_10 Base Address 0 Register................................................................................................. 27
3.1.12 Offset_20 Subsystem Vendor ID Register ....................................................................................... 27
3.1.13 Offset_22 Subsystem ID Register.................................................................................................... 27
3.1.14 Offset_30 Expansion Rom Base Address Register ......................................................................... 27
3.1.15 Offset_34 Cap_Ptr Register............................................................................................................. 27
3.1.16 Offset_3C Interrupt Line Register .................................................................................................... 28
3.1.17 Offset_3D Interrupt Pin Register...................................................................................................... 28
3.1.18 Offset_3E Min_Grant Register......................................................................................................... 28
3.1.19 Offset_3F Max Lat Register ............................................................................................................. 28
3.1.20 Offset_40 PCI_OHCI_Control Register ........................................................................................... 28
3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register .................................................................................. 29
3.1.22 Offset_62 Power Management Capabilities Register ...................................................................... 29
3.1.23 Offset_64 Power Management Control/Status Register .................................................................. 30
3.2 CardBus Mode Configuration Register ( CARD_ON=High ) ...................................................... 31
3.2.1 Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers)............................................ 32
3.2.2 Offset_28 Cardbus CIS Pointer ......................................................................................................... 33
3.2.3 Offset_80 CIS Area............................................................................................................................ 33
Preliminary Data Sheet S13925EJ2V0DS00
11
11 Page | ||
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