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PDF UPD7225 Data sheet ( Hoja de datos )
| Número de pieza | UPD7225 | |
| Descripción | PROGRAMMABLE LCD CONTROLLER/DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD7225
PROGRAMMABLE LCD CONTROLLER/DRIVER
The µPD7225 is a software-programmable LCD (Liquid Crystal Display) controller/driver. The µPD7225 can be
serially interfaced with the CPU in a microcomputer and can directly drive 2, 3, or 4-time division LCD. The µPD7225
contains a segment decoder which can generate specific segment patterns. In addition, the µPD7225 can be used to
control on/off (blinking) operation of a display.
FEATURES
• Can directly drive LCD
• Programmable time-division multiplexing
• Static drive
• Divide-by-2, 3, or -4 time division multiplexing
• Number of digits displayed
• 7-segment
Divide-by-4 time division ............... 16 digits
Divide-by-3 time division ............... 10 2/3 digits
Divide-by-2 time division ............... 8 digits
Static................................................. 4 digits
• 14-segment
Divide-by-4 time division ............... 8 digits
• Bias method
Static, 1/2, 1/3
• Segment decoder output
• 7-segment : Numeric characters 0 to 9, six symbols
• 14-segment : 36 alphanumeric characters, 13 symbols
• Blinking operation
• Multi-chip configuration possible
• 8-bit serials interface
75X series and 78K series compatible
• CMOS
• Single power supply
ORDERING INFORMATION
Part Number
µPD7225G00
µPD7225G01
µPD7225GB-3B7
µPD7225GC-AB6
Package
52-pin plastic QFP (14 × 14 mm)
52-pin plastic QFP (straight) ( 14 mm)
56-pin plastic QFP (10 × 10 mm)
52-pin plastic QFP (14 × 14 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14308EJ6V0DS00 (6th edition)
(O.D. No. IC-1555)
Date Published June 1999 N CP (K)
Printed in Japan
The mark shows major revised points.
©
1986, 1999
1 page  
µPD7225
1. PIN FUNCTIONS
1.1 SI (Serial Input)……Input
This pin is used for inputting serial data (commands/data). Data to be displayed as well as 19 deffernet
commands for controlling the operation of the µPD7225 can be input to this pin.
1.2 /SCK (Serial Clock)……Input
This pin is used for inputting the shift clock for serial data (SI input). The content of the SI input is read into the
serial register at the rising edge of this clock one bit at a time. /SCK input is effective when /CS = 0 and /BUSY = 1.
If /BUSY = 0, this input is ignored. If /CS = 1, this signal is ignored regardless of the /BUSY status.
1.3 C, /D (Command/Data)……Input
This input indicates whether the signal input from the SI pin is a command or data. A low level indicates data; a
high level indicates a command.
1.4 /BUSY……Tri-state output
This is an active-low output pin that is used to control serial data input disable/enable. A low level disables serial
data input; a high level enables serial data input. This pin becomes high impedance when /CS = 1.
1.5 /CS (Chip Select)……Input
When /CS is changed from high level to low level, the SCK counter in the µPD7225 is cleared and serial data
input is enabled. At the same time, the data pointer is initialized to address 0. When /CS is set to high level after
serial data is input, the contents of the data memory are transferred to the display latch and displayed on the LCD.
1.6 /SYNC (SYNChronous)……Input/Output
The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking
operation is synchronized in a multi-chip configuration.
When the µPD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (fCL) divided by four (refer to
Figure 1-1), and synchronizes the system clock (fCL/4) of the µPD7225. When the reset is released (/RESET =1), the
display timing of each µPD7225 is synchronized with the common drive signal timing shown in Figure 1-2.
Figure 1-1. /SYNC Pin Status During Reset (/RESET = 0)
fCL
/SYNC
Data Sheet S14308EJ6V0DS00
5
5 Page 
µPD7225
Figure 2-2. 14-Segment LCD
The 14-segment type LCD can be used only in the divide-by-4 time division mode. For the 14-segment LCD type,
connect segments and commons as follows:
SEGn + 3
SEGn + 2
,,,,,,,,,,,,,
,,,,,,,,,,,,,,
COM0
COM1
COM2
SEGn + 1 SEGn
COM3
a
f gh i b
jk
e lmn c
SEGn : h, i, k, n
SEGn + 1 : d, e, f
SEGn + 2 : a, b, c, DP
SEGn + 3 : g, j, l, m
COM0 : a, g, h
COM1 : b, i, j, f
COM2 : c, e, k, l
COM3 : d, m, n, DP
d DP
The following shows the input data and display pattern, and the configuration of the display data which is
automatically written into the data memory. For the 7-segment type, the lower 4 bits (D3 to D0) are decoded. For the
14-segment type, the input data and display pattern correspond to 8-bit ASCII code. The first address to which the
display data is written is indicated as address N.
Data Sheet S14308EJ6V0DS00
11
11 Page | ||
| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet UPD7225.PDF ] | |
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