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Número de pieza UPD70741GC-25-8EU
Descripción V821TM 32-/16-BIT MICROPROCESSOR
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD70741
V821TM
32-/16-BIT MICROPROCESSOR
The µPD70741 (V821) is a 32/16-bit RISC microprocessor that uses, as its processor core, the high-
performance 32-bit microprocessor µPD70732 (V810TM) designed for built-in control applications. It incorporates
peripheral functions such as a DRAM/ROM controller, 2-channel DMA controller, real-time pulse unit, serial
interface, and interrupt controller.
The V821, which offers quick real-time response, high-speed integer instructions, bit string instructions, and
floating-point instructions, is ideally suited to use in OA equipment such as printers and facsimiles, image
processing devices such as those used in navigation units, portable devices, and other devices demanding
excellent cost performance.
The functions are described in detail in the following User’s Manuals, which should be read before
starting design work.
• V821 User’s Manual Hardware
: U10077E
• V810 FamilyTM User’s Manual Architecture : U10082E
FEATURES
The V810 32-bit microprocessor is used as the CPU core
• Separate address/data bus
Address bus : 24 bits
Data bus : 16 bits
• Built-in 1-Kbyte instruction cache memory
• Pipeline structure of 1-clock pitch
• Internal 4-Gbyte linear address space
• 32-bit general-purpose registers: 32
Instructions ideal for various application fields
• Floating-point operation instructions and bit string
instructions
Interrupts controller
• Nonmaskable : 1 external input
• Maskable : 8 external inputs and 11 types of
internal sources
• Priorities can be specified in units of four groups.
Wait control unit
• Capable of CS control over four blocks in both memory
and I/O spaces.
• Linear address space of each block: 16M bytes
Memory access control functions
• Supports DRAM high-speed page mode.
• Supports page-ROM page mode.
DMA controller (DMAC): 2 channels
• Maximum transfer count: 65 536
• Two transfer types (fly-by (1-cycle) transfer and
2-cycle transfer)
• Three transfer modes (single transfer, single-
step transfer, and block transfer)
Serial interfaces : 2 channels
• Asynchronous serial interface (UART):
1 channel
• Synchronous serial interface (CSI):
1 channel
Real-time pulse unit
• 16-bit timer/event counter : 1 channel
• 16-bit interval timer
: 1 channel
Watchdog timer functions
Clock generator functions
Standby functions (HALT, IDLE, and STOP modes)
The information in this document is subject to change without notice.
Document No. U11678EJ4V0DS00 (4th edition)
Date Published June 1998 J CP(K)
Printed in Japan
The mark shows major revised points.
©
1996

1 page




UPD70741GC-25-8EU pdf
µPD70741
CONTENTS
1. PIN FUNCTIONS ........................................................................................................................
1.1 Port Pins .........................................................................................................................................
1.2 Non-Port Pins .................................................................................................................................
1.3 Pin I/O Circuits and Processing of Unused Pins ......................................................................
8
8
8
10
2. INTERNAL UNITS ...................................................................................................................... 12
2.1 Bus Interface Unit (BIU) ................................................................................................................ 12
2.2 Wait Control Unit (WCU) ............................................................................................................... 12
2.3 DRAM Controller (DRAMC) ........................................................................................................... 12
2.4 ROM Controller (ROMC) ................................................................................................................ 12
2.5 Interrupt Controller ........................................................................................................................ 12
2.6 DMA Controller (DMAC) ................................................................................................................ 12
2.7 Serial Interfaces (UART/CSI) ........................................................................................................ 12
2.8 Real-Time Pulse Unit (RPU) ......................................................................................................... 12
2.9 Watchdog Timer (WDT) ................................................................................................................. 13
2.10 Clock Generator (CG) .................................................................................................................... 13
2.11 Bus Arbitration Unit (BAU) ........................................................................................................... 13
2.12 Port .................................................................................................................................................. 13
3. CPU FUNCTIONS ....................................................................................................................... 14
3.1 Features .......................................................................................................................................... 14
3.2 Address Space ............................................................................................................................... 14
3.2.1 Memory map ................................................................................................................... 15
3.2.2 I/O map ............................................................................................................................ 16
3.3 CPU Register Set ........................................................................................................................... 17
3.3.1 Program register set ..................................................................................................... 18
3.3.2 System register set ........................................................................................................ 19
3.4 Built-in Peripheral I/O Registers .................................................................................................. 20
3.5 Data Types ...................................................................................................................................... 23
3.5.1 Data types ....................................................................................................................... 23
3.5.2 Data alignment ............................................................................................................... 25
3.6 Cache ............................................................................................................................................... 26
4. INTERRUPT/EXCEPTION HANDLING FUNCTIONS ............................................................... 27
4.1 Features .......................................................................................................................................... 27
5. WAIT CONTROL FUNCTIONS .................................................................................................. 30
5.1 Features .......................................................................................................................................... 30
5

5 Page





UPD70741GC-25-8EU arduino
Figure 1-1. Pin I/O Circuits
Type 1
IN
VDD
P-ch
N-ch
Type 5
Data
Output
disable
Input
enable
Type 2
IN
Schmitt trigger input with hysteresis characteristics
Type 8
Data
Output
disable
Type 4
Data
Output
disable
VDD
P-ch
N-ch
OUT
Push-pull output which can output high impedance
(Both the positive and negative channels are off.)
µPD70741
VDD
P-ch
N-ch
IN/OUT
VDD
P-ch
N-ch
IN/OUT
11

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