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PDF UPD705101 Data sheet ( Hoja de datos )
| Número de pieza | UPD705101 | |
| Descripción | 32-BIT MICROPROCESSOR | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD705101
V831TM
32-BIT MICROPROCESSOR
DESCRIPTION
The µPD70501 (V831) is a 32-bit RISC microprocessor for embedded control applications, with a high-performance
32-bit V830TM processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA
controller, real-time pulse unit, serial interface, and interrupt controller.
In addition to high interrupt response speed and optimized pipeline structure, the V831 offers sum-of-products
operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia
functions, and therefore, can provide high performance in multimedia systems such as internet/intra-net systems, car
navigation systems, high-performance televisions, and color FAXes.
Detailed explanations of the functions, etc. are given in the following user’s manuals. Be sure to read the
manuals before designing your systems.
V831 User’s Manual -Handware
: U12273E
V830 FamilyTM User’s Manual -Architecture : U12496E
FEATURES
• CPU function
• V830-compatible instructions
• Instruction cache
: 4 KB
• Instruction RAM
: 4 KB
• Data cache
: 4 KB
• Data RAM
: 4 KB
• Minimum number of instruction
execution cycles
: 1 cycle
• Number of general purpose
registers
: 32 bits × 32
• Memory space and I/O space
: 4 GB each
• Interrupt/exception function
• Non-maskable : External input : 1
• Maskable : External input : 8 (of which 4 are
multiplexed with internal sources)
Internal source: 11 types
• Bus control function
• Wait control function
• Memory access control function
• DMA controller : 4 channel
• Serial interface function
• Asynchronous serial interface (UART): 1 channel
• Clocked serial interface (CSI)
: 1 channel
• Dedicated baud rate generator (BRG) : 1 channel
• Timer/counter function
• 16-bit timer/event counter : 1 channel
• 16-bit interval timer
: 1 channel
• Port function
: 3 I/O ports
• Clock generation function : PLL clock synthesizer
• Standby function
: HALT and STOP modes
• Debug function
• Debug-dedicated synchronous serial
interface
: 1 channel
• Trace-dedicated interface
: 1 channel
The information in this document is subject to change without notice.
Document No. U12979EJ1V0DS00 (1st edition)
Date Published January 1998 N
Printed in Japan
©
1998
1 page  
µPD705101
CONTENTS
1. PIN FUNCTIONS LIST ......................................................................................................................... 6
2. INTERNAL UNITS ................................................................................................................................ 8
3. CPU FUNCTION ................................................................................................................................. 10
4. INTERRUPT/EXCEPTION PROCESSING FUNCTION ..................................................................... 11
5. BUS CONTROL FUNCTION .............................................................................................................. 13
6. WAIT CONTROL FUNCTION ............................................................................................................. 13
7. MEMORY ACCESS CONTROL FUNCTION ...................................................................................... 14
7.1 DRAM Control Function ............................................................................................................................ 14
7.2 Page-ROM Control Function ..................................................................................................................... 15
8. DMA FUNCTION ................................................................................................................................ 16
9. SERIAL INTERFACE FUNCTION ...................................................................................................... 18
9.1 Asynchronous Serial Interface (UART) ................................................................................................... 18
9.2 Clocked Serial Interface (CSI) ................................................................................................................... 20
9.3 Baud Rate Generator (BRG) ...................................................................................................................... 21
9.3.1 Configuration and function ................................................................................................................ 21
10. TIMER/COUNTER FUNCTION .......................................................................................................... 22
11. PORT FUNCTION .............................................................................................................................. 25
12. CLOCK GENERATION FUNCTION ................................................................................................... 27
13. STANDBY FUNCTION ........................................................................................................................ 28
14. RESET/NMI CONTROL FUNCTION .................................................................................................. 30
15. INSTRUCTIONS ................................................................................................................................. 31
15.1 Instruction Format ..................................................................................................................................... 31
15.2 Instructions (Listed Alphabetically) ......................................................................................................... 33
16. ELECTRICAL SPECIFICATIONS ...................................................................................................... 43
17. PACKAGE DRAWINGS ...................................................................................................................... 65
18. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 66
5
5 Page 
µPD705101
4. INTERRUPT/EXCEPTION PROCESSING FUNCTION
The features of the interrupt/exception processing function are as follows:
• Interrupt
• Non-maskable interrupt : 1 source
• Maskable interrupt : 15 sources
• Priority of the programmable interrupt can be specified in four levels
• Nesting interrupt can be controlled according to the priority
• Mask can be specified for each maskable interrupt request
• Valid edge of an external interrupt request can be specified
• Noise rejection circuit provided for the non-maskable interrupt pin (NMI)
• Exception
• Software exception : 32 sources
• Exception trap : 4 sources
The interrupt/exception sources are shown in Tables 4-1 and 4-2.
Table 4-1. Reset/Non-maskable Interrupt/Exception Source List
Type
Classification
Reset
Interrupt
Non-maskable
Interrupt
Software exception Exception
Exception trap
Exception
Source of Interrupt/Exception
NameNote 1
Cause
RESET
Reset input
NMI NMI input
TRAP 1nH
TRAP 0nH
TRAP instruction
TRAP instruction
NMI Dual exception
FAULT
Fatal exception
I-OPC
DIV0
Illegal instruction
code
Zero division
Exception Code
(ECR)
Handler
Address
Restore
PCNote 2
FFF0H
FFFFFFF0H Undefined
FFD0H
FFFFFFD0H next PCNote 3
FFBnH
FFFFFFB0H next PC
FFAnH
FFFFFFA0H
Note 4
FFFFFFD0H current PC
Not affected FFFFFFE0H
FF90H
FFFFFF90H
FF80H
FFFFFF80H
Notes 1. Handler names used in development tools or software.
2. The PC value saved to EIPC/FEPC/DPC when interrupt/exception processing is started.
3. Execution of all instructions cannot be stopped by an interrupt.
4. The exception code of an exception causing a dual exception.
Remark n = 0H to FH
11
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