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PDF UPD705100GJ-100-8 Data sheet ( Hoja de datos )

Número de pieza UPD705100GJ-100-8
Descripción V830TM 32-BIT MICROCONTROLLER
Fabricantes NEC 
Logotipo NEC Logotipo



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No Preview Available ! UPD705100GJ-100-8 Hoja de datos, Descripción, Manual

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD705100
V830TM
32-BIT MICROCONTROLLER
The µPD705100 (also called V830) is a microcontroller for incorporation use, which belongs to the V830 familyTM
of the NEC original V800 seriesTM microcontrollers. The V830 can achieve high cost-performance for multimedia
equipment, by integrating quick real-time responses, high-speed arithmetic/logical instructions, and functions suitable
for individual applications.
The following user’s manual describes details of the functions of the V830. Be sure to read it before
designing an application system.
V830 User’s Manual, Hardware : U10064E
V830 User’s Manual, Architecture : U12496E
FEATURES
High-performance 32-bit architecture for
incorporation use
• Built-in cache memory
Instruction cache : 4K bytes
Data cache
: 4K bytes
• Built-in RAM
Instruction RAM : 4K bytes
Data RAM
: 4K bytes
• One-clock-pitch pipeline structure
• 16-/32-bit instructions
• Separate buses for addresses and data
• 4G-byte linear addresses
• Thirty-two 32-bit general-purpose registers
• Hardware-interlocked register/flag hazard
• 16-level interrupt responses
16-bit bus fixing function
• 16-bit bus system construction
Instructions suitable for variable application
• Sum-of-products operation
• Saturable operation
• Branch prediction
• Concatenation shift
• Block transfer instructions
Power-saving mode
Maximum operating frequency
• 100 MHz (internal)
• 50/33 MHz (external)
CMOS operation, 3.3-V operation
ORDERING INFORMATION
Part number
µPD705100GJ-100-8EU
Package
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
The information in this document is subject to change without notice.
Document No. U11483EJ3V0DS00 (3rd edition)
Date Published January 1998 J CP(K)
Printed in Japan
The mark shows major revised points.
©
1995, 1996

1 page




UPD705100GJ-100-8 pdf
µPD705100
CONTENTS
1. PIN FUNCTIONS ........................................................................................................................
1.1 Pin Functions .................................................................................................................................
7
7
2. ADDRESS SPACE .....................................................................................................................
2.1 Memory Space ................................................................................................................................
2.2 I/O Space .........................................................................................................................................
8
8
10
3. 32-BIT BUS MODE ..................................................................................................................... 13
3.1 Relationship between External Accesses and Byte Enable Signals ..................................... 13
4. 16-BIT BUS MODE ..................................................................................................................... 14
4.1 16-Bit Bus Sizing ........................................................................................................................... 14
4.1.1 Byte/halfword access .................................................................................................... 14
4.1.2 Word access ................................................................................................................... 15
4.2 Relationship between External Access and Byte Enable Signals ......................................... 16
5. INTERRUPTS .............................................................................................................................. 17
5.1 Maskable Interrupts ....................................................................................................................... 17
5.2 Nonmaskable Interrupts ............................................................................................................... 18
5.3 Reset ................................................................................................................................................ 18
6. CLOCK CONTROLLER ............................................................................................................. 19
6.1 Operation Modes............................................................................................................................ 19
6.1.1 Sleep mode ..................................................................................................................... 19
6.1.2 Stop mode ....................................................................................................................... 19
7. INTERNAL MEMORY ................................................................................................................. 20
8. REGISTER SETS ....................................................................................................................... 21
8.1 Program Register Set .................................................................................................................... 21
8.1.1 General-purpose register set ....................................................................................... 21
8.1.2 Program counter (PC) ................................................................................................... 22
8.2 System Register Set ...................................................................................................................... 23
9. DATA SETS ................................................................................................................................ 24
9.1 Data Types ...................................................................................................................................... 24
9.1.1 Integers ........................................................................................................................... 25
9.1.2 Unsigned integers .......................................................................................................... 25
9.2 Data Alignment ............................................................................................................................... 25
10. ADDRESS SPACE .....................................................................................................................
10.1 Addressing Mode ...........................................................................................................................
10.1.1 Instruction addresses ...................................................................................................
10.1.2 Operand addresses .......................................................................................................
26
27
27
28
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UPD705100GJ-100-8 arduino
µPD705100
The cache function is not effective within the I/O space. When the chip select function is used, the area is used
as the 256M-byte image space represented by A2-A27.
Figure 2-3. Image Space Used When Chip Select Function is Used
FFFFFFFFH
C0000000H
BFFFFFFFH
80000000H
7FFFFFFFH
40000000H
3FFFFFFFH
00000000H
Internal I/O area
Image 11
Image 10
Image 9
Image 8
Image 7
Image 6
Image 5
Image 4
Image 3
Image 2
Image 1
Image 0
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11 Page







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