PDF VG4632321A Data sheet ( Hoja de datos )

Número de pieza	VG4632321A
Descripción	524/288x32x2-Bit CMOS Synchronous Graphic RAM
Fabricantes	Vanguard International Semiconductor
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No Preview Available ! VIS Overview Preliminary VG4632321A 524,288x32x2-Bit CMOS Synchronous Graphic RAM The VG4632321A SGRAM is a high-speed CMOS synchronous graphic RAM containing 32M bits. It is internally configured as a dual 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32 bit bank is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The VG4632321A provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, it features the write per bit and the masked block write functions. By having a programmable Mode register and special mode register, the system can choose the best suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, and when combined with special graphics functions result in a device particularly well suited to high performance graphics applications. Pin Assignment (Top View) Features • Fast access time from clock: 4.5/5/5.5/6/7ns • Fast clock rate: 222/200/183/166/143MHz • Fully synchronous operation • Internal pipelined architecture • Dual internal banks(512K x 32-bit x 2-bank) • Programmable Mode and Special Mode registers - CAS Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst Read Single Write - Load Color or Mask register • Burst stop function • Individual byte controlled by DQM0-3 • Block write and write-per-bit capability • Auto Refresh and Self Refresh • 2048 refresh cycles/32ms • Single + 3.3V ±0.3V power supply • Interface: LVTTL • JEDEC 100-pin Plastic QFP package DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS BS A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Key Specifications VG4632321A tCK Clock Cycle time(min.) tRAS Row Active time(min.) tAC Access time from CLK(max.) tRC Row Cycle time(min.) -4.5/-5/-5.5/-6/-7 4.5/5/5.5/6/7 ns 40/40/40/42/42 ns 4/4.5/5/5.5/6 ns 55/55/56.5/60/62 ns 80 DQ28 79 VDDQ 78 DQ27 77 DQ26 76 75 VSSQ DQ25 74 DQ24 73 72 VDDQ DQ15 71 DQ14 70 VSSQ 69 DQ13 68 DQ12 67 VDDQ 66 VSS 65 VDD 64 DQ11 63 DQ10 62 VSSQ 61 DQ9 60 DQ8 59 58 VDDQ NC 57 DQM3 56 DQM1 55 CLK 54 CKE 53 DSF 52 NC 51 A8/AP Document: Rev.1 Page 1 1 page VIS Preliminary VG4632321A 524,288x32x2-Bit CMOS Synchronous Graphic RAM Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note(1), (2)) Command State CKEn-1 CKEn DQM(7) BS A8 A0-7 CS RAS CAS WE DSF A9, A10 BankActivate & Masked Write Disable Idle(3) H X X V VVL L HHL BankActivate & Masked Write Enable Idle(3) H X X V VVL L HHH BankPrecharge Any H X X V L X L L H L L PrechargeAll Any H X X X H X L L H L L Write Active(3) H X X V LVLHL LL Block Write Command Active(3) H X X V LVLHL LH Write and AutoPrecharge Active(3) H X X V HVL H L L L Block Write and AutoPrecharge Active(3) H X X V HVL H L L H Read Active(3) H X X V LVLHLHL Read and AutoPrecharge Active(3) H X X V HVL H L HL Mode Register Set Idle H X X V L V L L L L L Special Mode Register Set Idle(5) H X X X XVL L L LH No-Operation Any H X X X X X L H H H X Burst Stop Active(4) H X X X XXL HHL L Device Deselect Any H X X X X X H X X X X AutoRefresh Idle H H X X X X L L L H L SelfRefresh Entry Idle H L X X X X L L L H L SelfRefresh Exit Idle (SelfRefresh) L H X X XXH X XXX L HHHX Clock Suspend Mode Entry Active H L X X XXX XXXX Power Down Mode Entry Any(6) H L X X XXH X XXX L HHHL Clock Suspend Mode Exit Active L H X X XXX XXXX Power Down Mode Exit Any L H X X X X H X X X X (Power- Down) L HHHL Data Write/Output Enable Active H X L X XXX XXXX Data Write/Output Disable Active H X H X XXX XXXX Note: 1. V = Valid X = Don’t Care L = Low level H = High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. The Special Mode Register Set is also available in Row Active State. 6. Power Down Mode can not entry in the burst operation. When this command assert in the burst cycle, device state is clock suspend mode. 7. DQM0-3 Document: Rev.1 Page 5 5 Page VIS Preliminary VG4632321A 524,288x32x2-Bit CMOS Synchronous Graphic RAM CLK COMMAND T0 T1 T2 T3 NOP WRITE A READ B NOP T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP CAS latency = 1 tCK1,DQ’s DIN A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS latency = 2 tCK2,DQ’s CAS latency = 3 tCK3,DQ’s DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 DIN A0 don’t care don’t care Input data for the write is masked DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from DQ’ s at least one clock cycle before the Read data appears on the outputs to avoid data contention Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without auto pre- charge function should be issued m cycles after the clock edge at which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). CLK DQM T0 COMMAND WRITE ADDRESS DQ BANK COLn DIN n T1 T2 T3 T4 T5 T6 NOP Precharge tRP NOP NOP Activate NOP BANK (S) tWR DIN n+1 ROW :don’t care Write to Precharge When Burst-Read and Single-Write mode is selected , the write burst length is 1 regardless of the read burst length (refer to Figures 21 and 22 in Timing Waveforms). 8 Block Write command (RAS = “H” , CAS = “L” , WE = “L”, DSF = “H” , BS =Bank , A8 = “L” , A3-A7 = Column Address, DQ0-DQ31 = Column Mask) The block writes are non-burst accesses that write to eight column locations simultaneously. A single data value, which was previously loaded in the Color register, is written to the block of eight consecutive column locations addressed by inputs A3-A7. The information on the DQs which is registered coincident with the Block Write command is used to mask specific column/byte combinations within the block . The mapping of the DQ inputs to the column/byte combinations is shown in following table. Document: Rev.1 Page 11 11 Page

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