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PDF VG4616322BQ-7 Data sheet ( Hoja de datos )

Número de pieza VG4616322BQ-7
Descripción 262/144x32x2-Bit CMOS Synchronous Graphic RAM
Fabricantes Vanguard International Semiconductor 
Logotipo Vanguard International Semiconductor Logotipo



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VIS
Overview
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It
is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by
256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4616321(2) provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page,
with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row pre-
charge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh
are easy to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
• Fast access time from clock: 4.5/5/5.5ns
• Fast clock rate: 200/166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(256K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single + 3.3V ±0.3V power supply
• Input Reference Voltage : Vref = 1.5V ± 0.2V
• Interface: LVTTL and SSTL_3
• JEDEC 100-pin Plastic QFP package
Document:1G5-0145
Rev.1
Page 1

1 page




VG4616322BQ-7 pdf
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
23,56,24,
57
DQM0-
DQM3
Input
Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer
controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.
Input data is masked when DQM is sampled HIGH during a write cycle. Output data
is masked (two-clock latency) when DQM is sampled HIGH during a read cycle.
DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8,
and DQM0 masks DQ7-DQ0.
97,98,100,
1,3,4,6,7,
60,61,63,
64,68,69,
71,72,9,
10,12,13,
17,18,20,
21,74,75,
77, 78,80,
81, 83, 84
DQ0-
DQ31
Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive
Output edges of CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also
serve as column/byte mask inputs during Block Writes.
30,36-45, NC
52,86-95
- No Connect: These pins should be left unconnected.
58 NC/Vref -/Input No connect/Input Voltage Reference : It must be unconnected when the LVTTL
interface is used in the SGRAM. It must be applied to Vref (1.5V) when the SSTL-3
interface is used in the SGRAM.
2,8,14,22,
59,67,73,
79
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
5,11,19,
62,70,76,
82,99
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
15,35,65, VDD Supply Power Supply: +3.3V ±0.3V
96
16,46,66, VSS Supply Ground
85
Document:1G5-0145
Rev.1
Page 5

5 Page





VG4616322BQ-7 arduino
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
DSF
DQ
BankActivate CK
command
DQM0
DRAM
CELL
MR7
MR6
MR5
MR4
DQ7
DQ6
DQ5
DQ4
MR3
MR2
MR1
DQ3
DQ2
DQ1
MR0
DQ0
0 = Masked
1 = Not Masked
Note: Only lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without auto precharge function may be interrupted by a subsequent Write/Block
Write, BankPrecharge/PrechargeAll, or Read command before the end of burst length. The interrupt
comes from Write/Block Write command can occur on any clock cycle following the previous Write
command ( refer to the following figure).
T0 T1 T2 T3 T4 T5 T6
T7 T8
CLK
COMMAND NOP
DQ’s
WRITE A WRITE B
1 Clk Interval
DIN A0
DIN B0
NOP
DIN B1
NOP
NOP
DIN B2
DIN B3
NOP
NOP
NOP
Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should
be issued one cycle after the clock edge at which the last data-in element is registered. In
order to avoid data contention, input data must be removed from the DQs at least one clock
cycle before the first read data appears on the outputs (refer to the following figure). Once the
Read command is registered, the data inputs will be ignored, and writes will not be executed.
Document:1G5-0145
Rev.1
Page 11

11 Page







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