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PDF VG36646141BT-7 Data sheet ( Hoja de datos )

Número de pieza VG36646141BT-7
Descripción CMOS Synchronous Dynamic RAM
Fabricantes Vanguard International Semiconductor 
Logotipo Vanguard International Semiconductor Logotipo



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VIS
Description
Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 1,048,576 - word x 16-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time : 8/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,&Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A12 & A13 (Bank select)
• Each Bank can operate simultaneously and independently
• LVTTL compatible I/O interface
• Random column access in every cycle
• X16 organization
• Input/Output controlled by LDQM and UDQM
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0127
Rev2
Page 1

1 page




VG36646141BT-7 pdf
VIS
Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
VG36641641B
-7 -8 Unit
Min Max Min Max
Operating current
Precharge standby
current in power
down mode
ICC1
Burst length = 1
CL = 3
One bank active
CL = 2
tRC tRC(MIN.), Io = 0mA
ICC 2P CKE VIH(MAX.) tCK = 10ns
ICC 2PS CKE VIH(MAX.) tCK =
130
130
2
2
130 mA
130
2 mA
2
Precharge standby current ICC 2N CCKKEE VIH(MIN.) tCK = 10ns.
in Nonpower down mode
CCKSE VIH(MIN.)
Input signals are changed one
time during 2 CLK cycles.
25 25 mA
ICC 2NS CCKKEE VVIH(MIN.), tCK =
CLK VIL(MAX.)
Input signals are stable.
77
Active standby current in
power down mode
Active standby current in
Nonpower down mode
ICC 3P CKE VIL(MAX.), tCK = 10ns
ICC 3PS CKE VIL(MAX.), tCK =
ICC 3N CCKKEE VIH(MAX.), tCK = 10ns
CCKSE VIH(MIN.)
Input signals are changed
one time during 2CLKs.
7 7 mA
55
40 40 mA
ICC 3NS CCKKEE VIH(MIN.) tCK =
CLE VIL(MAX.)
Input signals are stable.
20 20
Operating current
(Burst mode)
ICC4
CtKCKE VtCK(MIN.), Io = 0mA CL = 3
All banks Active
CL = 2
170
135
170 mA
120
Refresh current
Self refresh current
ICC5
ICC6
tRC tRC(MIN.)
CKE 0.2V
220 200 mA
1 1 mA
Input leakage current ILI CVKINE V0, VIN VDD + 0.3V
Pins not under test = 0V
- 5 5 -5 5 µA
Output leakage current ILO
VCOKUTE V0, VOUT VDD (MAX)
DQ# in H - Z., Dout disabled
- 5 5 -5 5 µA
Output Low Voltage
VOL IOL = 2mA
0.4 0.4 mA
Output High Voltage
VOH IOH = -2mA
2.4 2.4 mA
Notes
1
2
3
4
4
Notes: 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC1 is measured on condition that addresses are changed only one
time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC4 is measured on condition that addresses are changed only one
time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
4. For LVTTL compatible, VG36648041.
Document : 1G5-0127
Rev2
Page 5

5 Page





VG36646141BT-7 arduino
VIS
Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
Current state
Read with auto
precharge
Write with auto
precharge
Precharging
Row activating
CS RAS CA WE Address
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
Command
Action
DESL
NOP
Continue burst to end Precharging
Continue burst to end Precharging
BST ILLEGAL
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
ILLEGAL
PEF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
Continue burst to end write
recovering with auto precharte
NOP
Continue burst to end write
recovering with auto precharge
BST ILLEGAL
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
ILLEGAL
REF/SELF
ILLEGAL
MRS
DESL
NOP
BST
ILLEGAL
Nop Enter idle after tRP
Nop Enter idle after tRP
Nop Enter idle after tRP
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
Nop Enter idle after tRP
REF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
NOP
BST
Nop Enter row active after tRCD
Nop Enter row active after tRCD
Nop Enter row active after tRCD
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
ILLEGAL
REF/SELF
ILLEGAL
MRS
ILLEGAL
(2/3)
Notes
11
11
3,11
3,11
11
11
3,11
3,11
3
3
3
3
3
3,9
3
Document : 1G5-0127
Rev2
Page 11

11 Page







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