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PDF VG36643241BT-10 Data sheet ( Hoja de datos )

Número de pieza VG36643241BT-10
Descripción CMOS Synchronous Dynamic RAM
Fabricantes Vanguard International Semiconductor 
Logotipo Vanguard International Semiconductor Logotipo



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VIS
Description
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 -
bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced
submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is
packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time : 8/10 for LVTTL
• High speed clock cycle time : 8/10 for SSTL - 3
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual Internal banks controlled by A11 (Bank select) for VG36643211(2)
• Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2)
• Each Banks can operate simultaneously and independently
• LVTTL compatible I/O interface for VG36643211 and VG36643241
• SSTL - 3 compatible I/O interface for VG36643212 and VG36643242
• Random column access in every cycle
• x32 organization
• Input/Output controlled by DQM0 ~ 3
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
Document : 1G5-0099
Rev.1
Page 1

1 page




VG36643241BT-10 pdf
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Absolute Maximum D.C. Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 to + 4.6
V
Supply voltage relative to Vss
VDD, VDDQ
-0.5 to + 4.6
V
Short circuit output current
IOUT
50 mA
Power dissipation
PD 1.0 W
Operating temperature
TOPT
0 to + 70
°C
Storage temperature
TSTG
-55 to + 125
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Symbol
Min
Input High Voltage
VIH 2.0
Input Low Voltage
VIL VSSQ -2.0
Max
VDDQ + 2.0
0.8
Unit
V
V
Notes
2
2
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Symbol
Min
Supply Voltage
VDD, VDDQ
3.0
Input High Voltage, all inputs
VIH 2.0
Input Low Voltage, all inputs
VIL -0.3
Typ
3.3
-
-
Max
3.6
VDD + 0.3
0.8
Unit
V
V
V
Recommended DC Operating Conditions for SSTL - 3 Interface
Parameter
Symbol
Min
Typ
Supply Voltage
VDD, VDDQ
3.0
3.3
Supply Voltage (Ground)
VSS, VSSQ
0
-
Reference Voltage
VREF 1.3 1.5
Termination Voltage
VTT
VREF -005
VREF
Input High Voltage, all inputs
VIH(dc)
VREF + 0.2
-
Input Low Voltage, all inputs
VIH(dc)
-0.3
-
Max
3.6
0
1.7
VREF + 0.05
VDD + 0.3
VREF -0.2
Unit
V
V
V
V
V
V
Capacitance
(Ta = 25°C, f = 1MHZ)
Parameter
Symbol Typ Max Unit Notes
Input capacitance (Address)
Input capacitance (all input pins
except address pins & data pins.)
CI1 - 4 pF 1
CI2 - 4 pF 1
Data input/output capacitance
CI/O - 5 pF
Notes : 1. Capacitance measured with effective capacitance measuring method.
2. The overshoot and undershoot voltage duration is 3ns with no input clamp diodes.
1
Document : 1G5-0099
Rev.1
Page 5

5 Page





VG36643241BT-10 arduino
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
2.4 Operative Command Table Notes 1
Current state CS RAS CAS WE Address
Idle H X X X X
L H H XX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BR, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
Row active H X X X X
L H H XX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
Read
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Write
L L L L Op - Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
(1/3)
Command
Action
Notes
DESL
Nop or Power down
2
NOP or BST Nop or Power down
2
READ/READA ILLEGAL
3
WRIT/WRITA ILLEGAL
3
ACT
Row active
PRE/PALL
Nop
REF/SELF
Refresh or Self refresh
4
MPS
Mode register access
DESL
Nop
NOP or BST Nop
READ/READA Begin read : Determine AP
5
WRIT/WRITA Begin write : Determine AP
5
ACT
ILLEGAL
3
PRE/PALL
Precharge
6
REF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
Continue burst to end Row active
NOP
BST
Continue burst to end Row active
Burst stop Row active
READ/READA Term burst, new read : Determine AP 7
WRIT/WRITA Term burst, start write : Determine AP 7,8
ACT
ILLEGAL
3
PRE/PALL
Term burst, precharging
REF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
Continue burst to end write recovering
NOP
Continue burst to end write recovering
BST Burst stop Row active
READ/READA Term burst, start read : Determine AP 7,8
WRIT/WRITA Term burst, new write : Determine AP 7
ACT
ILLEGAL
3
PRE/PALL
Term burst, precharging
9
REF/SELF
ILLEGAL
MRS
ILLEGAL
Document : 1G5-0099
Rev.1
Page 11

11 Page







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