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PDF VFC100AG Data sheet ( Hoja de datos )

Número de pieza VFC100AG
Descripción Synchronized VOLTAGE-TO-FREQUENCY CONVERTER
Fabricantes Burr-Brown Corporation 
Logotipo Burr-Brown Corporation Logotipo



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No Preview Available ! VFC100AG Hoja de datos, Descripción, Manual

® VFC100
FPO
Synchronized
VOLTAGE-TO-FREQUENCY CONVERTER
FEATURES
q FULL-SCALE FREQUENCY SET BY
SYSTEM CLOCK; NO CRITICAL
EXTERNAL COMPONENTS REQUIRED
q PRECISION 10V FULL-SCALE INPUT,
0.5% max GAIN ERROR
q ACCURATE 5V REFERENCE VOLTAGE
q EXCELLENT LINEARITY:
0.02% max at 100kHz FS
0.1% max at 1MHz FS
q VERY LOW GAIN DRIFT: 50ppm/°C
APPLICATIONS
q A/D CONVERSION
q PROCESS CONTROL
q DATA ACQUISITION
q VOLTAGE ISOLATION
DESCRIPTION
The VFC100 voltage-to-frequency converter is an
important advance in VFCs. The well-proven charge
balance technique is used; however, the critical reset
integration period is derived from an external clock
frequency. The external clock accurately sets an out-
put full-scale frequency, eliminating error and drift
from the external timing components required for
other VFCs. A precision input resistor is provided
which accurately sets a 10V full-scale input voltage.
In many applications the required accuracy can be
achieved without external adjustment.
The open collector active-low output provides fast fall
time on the important leading edge of output pulses,
and interfaces easily with TTL and CMOS circuitry.
An output one-shot circuit is particularly useful to
provide optimum output pulse widths for optical cou-
plers and transformers to achieve voltage isolation. An
accurate 5V reference is also provided which is useful
for applications such as offsetting for bipolar input
voltages, exciting bridges and sensors, and autocali-
bration schemes.
VIN
Non-Inverting
Input
C INT
5
– Comparator
VOUT
Input
4 14
Clock
Input
10
7 RIN
Integrator
Amplifier
6 20k
SW1
Comparator
Clocked
Logic
+VCC
1
Output
One-Shot
11
fOUT
12 Digital
Common
1mA
–VCC
13
Analog
Common
15
+ Comparator
Input
5V
Reference
16
VREF
9
COS
8
–VCC
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1984 Burr-Brown Corporation
PDS-547H
Printed in U.S.A. June, 1995

1 page




VFC100AG pdf
C INT
54
IIN
VIN
7 RIN
Integrator
6 20k
S1
FC Clock
TTL/CMOS
14 10
Comparator
Clocked
Logic
1mA
I1
–VCC
13
Analog
Ground
15
5V
Reference
16
FIGURE 1. Circuit Diagram for Voltage-to-Frequency Mode.
0.1µF +VCC
1
+VCC
Output
One-Shot
+VL 0.1µF
11
fOUT
12
–VCC
Digital
Ground
9
+VCC
8 0.1µF
–VCC
Clock
Integrator 5V
fO
FIGURE 2. Timing Diagram for Voltage-to-Frequency Mode.
the necessary transitions of the clock). Output pulses are
thus made to align with rising edges of the external clock.
This causes the instantaneous output frequency to be a
subharmonic of the clock frequency. The average frequency,
however, will be an accurate analog of the input voltage.
A full scale input of 10V (or an input current of 0.5mA)
causes a nominal output frequency equal to half the clock
frequency. The transfer function is
fOUT = (VIN/20V) fCLOCK.
Figure 3 shows the transfer function graphically. Note that
inputs above 10V (or 0.5mA) do not cause an increase in the
output frequency. This is an easily detectable indication of
an overrange input. In the overrange condition, the integra-
tor amplifier will ramp to its negative output swing limit.
fFS = fCLOCK /2
f OUT
When the input signal returns to within the linear range, the
integrator amplifier will recover and begin ramping upward
during the reset period.
INSTALLATION AND
OPERATING INSTRUCTIONS
The integrator capacitor CINT (see Figure 1) affects the
magnitude of the integrator voltage waveform. Its absolute
accuracy is not critical since it does not affect the transfer
function. This allows a wide range of capacitance to produce
excellent results. Figure 4 facilitates choosing an appropriate
10µ
0.1µ
0.01µ
1000p
Integrator Swing*
+100mV
–75mV
+1V
–0.75V
+2.5V
–1.9V
0 VIN 10V
0 IIN 0.5mA
100p
100
1k
10k 100k
1M
Full-Scale Frequency (Hz)
10M
* This is the maximum swing of the integrator output voltage
referred to the comparator noninverting input voltage.
FIGURE 3. Transfer Function for Voltage-to-Frequency Mode. FIGURE 4. Integrator Capacitor Selection Graph.
5 VFC100
®

5 Page





VFC100AG arduino
FREQUENCY-TO-VOLTAGE MODE
The VFC100 can also function as a frequency-to-voltage
converter by supplying an input frequency to the comparator
input as shown in Figure 16. The input resistor, RIN, is
connected as a feedback resistor. The voltage at the integra-
tor amp output is proportional to the ratio of the input
frequency to the clock frequency. The transfer function is
VOUT = (FIN/fCLOCK) 20V.
This transfer function is complementary to the voltage-to-
frequency mode transfer function, making voltage-to-fre-
quency-to-voltage conversions simple and accurate.
Direct coupling of the input frequency to the comparator is
easily accomplished by driving both comparators with
complementary frequency input signals. Alternatively, one
of the comparator inputs can be biased at half the logic
voltage (using VREF and a voltage divider) and the other
input driven directly.
The proper timing of the input frequency waveform is shown
in Figure 16. The input pulse should go low for one clock
cycle, centered around a falling edge of the clock. The
minimum acceptable input pulse width must fall no later
than 200ns before a negative clock edge and rise no sooner
> 3V
+VCC
54
7.5V to
28.5V
> –0.2V
7 RIN
6
< 0.1V
> 7.5V > –7.5V
–VCC
13
7.5V to 28.5V
–VCC
–VCC + 4 to +VCC – 2
–VCC + 2 to +VCC – 2
14 10
1
+VCC
Clocked
Logic
Output
One-Shot
11 > 4V
–0.5V
to 30V
12
15V to
36V
5V
Reference
15 16
5V
–VCC + 4 to +VCC – 2
–VCC
98
+VCC or COS
> 2V
FIGURE 13. Relationships of Allowable Voltages.
CMOS Inverters
fC 200kHz
÷ 4000
22k
22
68pF
(M = 4000)
+15VDC
C1 0.1µF
5 4 14
10
0.1µF
1
+VCC
0 to 10V 7 RIN
Input
6
Clocked
Logic
Output
One-Shot
DQ
CQ
4000 Counts
0.1µF
+VL
11
fO = 0 to 100kHz
12
To Processor
µP or Display
Reset
Counter “N”
Maximum Count:
N = M/2 = 2000
–VCC
13
5V
Reference
–VCC
Logic
Ground
15 16 9 8
0.05µF
+15VDC
0.1µF
–15VDC
FIGURE 14. Diagram of a Voltage-to-Frequency Converter and Counter System.
11
Computed Result
VIN' = 20V x (N/M)
VFC100
®

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