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PDF VE28F008 Data sheet ( Hoja de datos )

Número de pieza VE28F008
Descripción 8 MBIT (1 MBIT x 8) FLASH MEMORY
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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No Preview Available ! VE28F008 Hoja de datos, Descripción, Manual

VE28F008
8 MBIT (1 MBIT x 8) FLASH MEMORY
Y High-Density Symmetrically Blocked
Architecture
Sixteen 64 Kbyte Blocks
Y Avionics Temperature Range
b40 C to a125 C
Y Extended Cycling Capability
10K Block Erase Cycles
160K Block Erase
Cycles per Chip
Y Automated Byte Write and Block Erase
Command User Interface
Status Register
Y System Performance Enhancements
RY BY Status Output
Erase Suspend Capability
Y Very High-Performance Read
95 ns Maximum Access Time
Y SRAM-Compatible Write Interface
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Industry Standard Packaging
40-Lead TSOP
Y ETOXTM III Nonvolatile Flash
Technology
12V Byte Write Block Erase
Y Independent Software Vendor Support
Microsoft Flash File System (FFS)
Intel’s VE28F008 8-Mbit Flash FileTM Memory revolutionizes the design of high performance and durable
mass storage memory systems for the Industrial Avionics and Military markets With its innovative features
like low power blocked architecture high read write performance and expanded temperature range any
design or mission is free from the dependence on battery backed up memory or highly sensitive and slow
rotating media drives
Using the VE28F008 in a PCMCIA 2 1 Flash Memory card ATA drive or any size or shape module will allow
data application or operating systems to be updated or collected anywhere and at anytime This data on
demand feature ensures protection from obsolesce through field or in system software updates
The VE28F008’s highly integrated Command User Interface and Write State Machine decreases the size and
complexity of system software while providing high read write and erase performance The sixteen separately
erasable 64 Kbyte blocks along with a multiple write data protection system provides assurance that highly
important data will be available when needed
The VE28F008 is offered in a 40-lead TSOP (Thin Small Outline Package) which is capable of performing in
temperatures from b40 C to a125 C It employs advanced CMOS circuitry for systems requiring low power
consumption and noise immunity The VE28F008’s 95 ns access time provides superior performance when
compared to magnetic mass storage
Manufactured on Intel’s 0 8 micron ETOXTM III process the VE28F008 provides the highest levels of quality
reliability and cost effectiveness
Microsoft is a trademark of Microsoft Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
May 1994
Order Number 271305-001

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VE28F008 pdf
VE28F008
271305 – 3
Figure 3 VE28F008 Array Interface to Intel386TM SL Microprocessor Superset through PI Bus
(Including RY BY Masking and Selective Powerdown) for DRAM Backup during System SUSPEND
Resident O S and Applications and Motherboard Solid-State Disk
PRINCIPLES OF OPERATION
The VE28F008 includes on-chip write automation to
manage write and erase functions The Write State
Machine allows for 100% TTL-level control inputs
fixed power supplies during block erasure and byte
write and minimal processor overhead with RAM-
like interface timings
After initial device powerup or after return from
deep powerdown mode (see Bus Operations) the
VE28F008 functions as a read-only memory Manip-
ulation of external memory-control pins allow array
read standby and output disable operations Both
Status Register and intelligent identifier can
also be accessed through the Command User Inter-
face when VPP e VPPL
This same subset of operations is also available
when high voltage is applied to the VPP pin In addi-
tion high voltage on VPP enables successful block
erasure and byte writing of the device All functions
associated with altering memory contents byte
write block erase status and intelligent identifier
are accessed via the Command User Interface and
verified thru the Status Register
Commands are written using standard microproces-
sor write timings Command User Interface contents
serve as input to the WSM which controls the block
5

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VE28F008 arduino
VE28F008
EXTENDED BLOCK ERASE BYTE
WRITE CYCLING
Intel has designed extended cycling capability into
its ETOX flash memory technologies The
VE28F008 is designed for 10 000 byte write block
erase cycles on each of the sixteen 64 Kbyte blocks
Low electric fields advanced oxides and minimal ox-
ide area per cell subjected to the tunneling electric
field combine to greatly reduce oxide stress and the
probability of failure A 20 Mbyte solid-state drive us-
ing an array of VE28F008s has a MTBF (Mean Time
Between Failure) of 3 33 million hours(1)
AUTOMATED BYTE WRITE
The VE28F008 integrates the Quick-Pulse program-
ming algorithm of prior Intel Flash devices on-chip
using the Command User Interface Status Register
and Write State Machine (WSM) On-chip integration
dramatically simplifies system software and provides
processor interface timings to the Command User
Interface and Status Register WSM operation inter-
nal verify and VPP high voltage presence are moni-
tored and reported via the RY BY output and appro-
priate Status Register bits Figure 5 shows a system
software flowchart for device byte write The entire
sequence is performed with VPP at VPPH Byte write
abort occurs when RP transitions to VIL or VPP
drops to VPPL Although the WSM is halted byte
data is partially written at the location where byte
write was aborted Block erasure or a repeat of byte
write is required to initialize this data to a known
value
AUTOMATED BLOCK ERASE
As above the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally includ-
ing all preconditioning of block data WSM opera-
tion erase success and VPP high voltage presence
are monitored and reported through RY BY and the
Status Register Additionally if a command other
than Erase Confirm is written to the device following
Erase Setup both the Erase Status and Byte Write
Status bits will be set to ‘‘1’’s When issuing the
Erase Setup and Erase Confirm commands they
should be written to an address within the address
range of the block to be erased Figure 6 shows a
system software flowchart for block erase
Erase typically takes 1 6 seconds per block The
Erase Suspend Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed A system software flowchart is
shown in Figure 7
The entire sequence is performed with VPP at VPPH
Abort occurs when RP transitions to VIL or VPP falls
to VPPL while erase is in progress Block data is
partially erased by this operation and a repeat of
erase is required to obtain a fully erased block
DESIGN CONSIDERATIONS
Three-Line Output Control
The VE28F008 will often be used in large memory
arrays Intel provides three control inputs to accom-
modate multiple memory connections Three-line
control provides for
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these control inputs an address
decoder should enable CE while OE should be con-
nected to all memory devices and the system’s
READ control line This assures that only selected
memory devices have active outputs while deselect-
ed memory devices are in Standby Mode Finally
RP should either be tied to the system RESET or
connected to VCC if unused
RY BY and Byte Write Block Erase
Polling
RY BY is a full CMOS output that provides a hard-
ware method of detecting byte write and block erase
completion It transitions low time tWHRL after a
write or erase command sequence is written to the
VE28F008 and returns to VOH when the WSM has
finished executing the internal algorithm
RY BY can be connected to the interrupt input of
the system CPU or controller It is active at all times
not tri-stated if the VE28F008 CE or OE inputs are
brought to VIH RY BY is also VOH when the device
is in Erase Suspend or deep powerdown modes
(1)Assumptions 10 Kbyte file written every 10 minutes (20 Mbyte array) (10 Kbyte file) e 2 000 file writes before erase required
(2000 files writes erase) c (10 000 cycles per VE28F008 block) e 20 million file writes
(20 c 106 file writes) c (10 min write) c (1 hr 60 min) e 3 33 c 106 MTBF
11

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