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PDF V62C3162048LL-55T Data sheet ( Hoja de datos )

Número de pieza V62C3162048LL-55T
Descripción Ultra Low Power 128K x 16 CMOS SRAM
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo



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No Preview Available ! V62C3162048LL-55T Hoja de datos, Descripción, Manual

Features
• Low-power consumption
- Active: 65mA ICC at 35ns
- Stand-by: 10 µA (CMOS input/output)
2 µA (CMOS input/output, L version)
• 35/45/55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.7V to3.3V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOP II / 48-fpBGA
V62C3162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Functional Description
The V62C3162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
memory expansion is provided by an active LOW (CE)
and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
TSOPII / 48-fpBGA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
Pre-Charge Circuit
Memory Array
1024 X 2048
Vcc
Vss
Data
Cont I/O Circuit
Data
Cont Column Select
A10 A11 A12 A13 A14 A15 A16
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O1 7
I/O2 8
I/O3 9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A16 18
A15 19
A14 20
A13 21
A12 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
REV. 1.2 May 2001 V62C3162048L(L)
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V62C3162048LL-55T pdf
V62C3162048L(L)
DC Operating Characteristics (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Parameter
Input Leakage Current
Output Leakage
Current
Sym Test Conditions
IILII
Vcc = Max,
Vin = Gnd to Vcc
IILOI
CE = VIH or Vcc= Max,
VOUT = Gnd to Vcc
-35 -45 Unit
Min Max Min Max
-1-1
µA
-1-1
µA
Operating Power
Supply Current
ICC CE = VIL , VIN = VIH or VIL ,
-
5
-
5
mA
IOUT = 0
Average Operating
Current
ICC1 IOUT = 0mA,
Min Cycle, 100% Duty
- 65 - 60 mA
ICC2 CE < 0.2V
IOUT = 0mA,
- 3 - 3 mA
Cycle Time=1µs, Duty=100%
Standby Power Supply ISB CE = VIH
Current (TTL Level)
- 0.5 - 0.5 mA
Standby Power Supply ISB1 CE > Vcc - 0.2V
Current (CMOS Level)
VIN < 0.2V or
VIN > Vcc- 0.2V
- 10 - 10
L- 2 - 2
µA
µA
Output Low Voltage
VOL IOL = 2 mA
- 0.4 - 0.4
V
Output High Voltage
VOH IOH = -2 mA
2.4 - 2.4 -
V
REV. 1.2 May 2001 V62C3162048L(L)
5

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V62C3162048LL-55T arduino
V62C3162048L(L)
Data Retention Characteristics (L Version Only)(1)
Parameter
VCC for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time(2)
Symbol
VDR
ICCDR
tCDR
tR
Test Condition
CE > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V
Min
2.0
-
0
tRC
Max
-
1
-
-
Unit
V
µA
ns
ns
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
VCC
CE
Vcc_typ
tCDR
VIH
Data Retention Mode
VDR > 2.0V
VDR
Vcc_typ
tR
VIH
Notes (Write Cycle)
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is High for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
REV. 1.2 May 2001 V62C3162048L(L)
11

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