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PDF V61C31161024-12T Data sheet ( Hoja de datos )
| Número de pieza | V61C31161024-12T | |
| Descripción | 64K x 16 HIGH SPEED STATIC RAM | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V61C31161024
64K x 16 HIGH SPEED
STATIC RAM
PRELIMINARY
INFORMATION
Features
s High-speed: 10, 12, 15 ns
s All inputs and outputs directly TTL compatible
s Three state outputs
s Single 3.3V ± 10% Power Supply
s Packages
– 44-pin TSOP (Standard)
– 44-pin 400 mil SOJ
s Low Power Consumption
– Active: 140mA
– Standby: 2mA (CMOS)
Description
The V61C31161024 is a 1,048,576-bit static
random-access memory organized as 65,536
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
A1
A7
A8
A9
I/O0
I/O15
UBE
LBE
OE
WE
CE
Functional Block Diagram
Row
Decoder
Memory Array
VCC
GND
Input
Data
Circuit
Column I/O
Column Decoder
Control
Circuit
A0 A10
A15
6131161024-01
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
V61C31161024 Rev. 0.5 August 1999
Package Outline
TK
••
Access Time (ns)
10 12 15
•••
1
Temperature
Mark
Blank
1 page  
MOSEL VITELIC
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Parameter
Name
tRC
tAA
tACS
tBA
tOE
tCLZ
tBLZ
tOLZ
tCHZ
tOHZ
tBHZ
tOH
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
UBE, LBE Access Time
Output Enable to Output Valid
Chip Enable to Output in Low Z
UBE, LBE to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
UBE, LBE to Output in High Z
Output Hold from Address Change
Write Cycle
Parameter
Name
tWC
tCW
tAS
tAW
tWP
tAH
tWHZ
tWLZ
tDW
tDH
tBW
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Address Hold from End of Write
Write to Output High-Z
Write to Output Low Z
Data Setup to End of Write
Data Hold from End of Write
UBE, LBE to End of Write
V61C31161024
-10 -12 -15
Min. Max. Min. Max. Min. Max. Unit
10 — 12 — 15 — ns
— 10 — 12 — 15 ns
— 10 — 12 — 15 ns
— 5 — 6 — 7 ns
— 5 — 6 — 7 ns
2 — 3 — 3 — ns
0 — 0 — 0 — ns
0 — 0 — 0 — ns
0 5 0 6 0 7 ns
0 5 0 6 0 7 ns
0 5 0 6 0 7 ns
2 — 3 — 3 — ns
-10 -12 -15
Min. Max. Min. Max. Min. Max. Unit
10 — 12 — 15 — ns
7 — 8 — 10 — ns
0 — 0 — 0 — ns
7 — 8 — 10 — ns
7 — 8 — 10 — ns
0 — 0 — 0 — ns
0 5 0 6 0 7 ns
3 — 3 — 5 — ns
5 — 6 — 7 — ns
0 — 0 — 0 — ns
7 — 8 — 10 — ns
V61C31161024 Rev. 0.5 August 1999
5
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