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PDF V61308S Data sheet ( Hoja de datos )

Número de pieza V61308S
Descripción Accurate Power Surveillance and Software Monitoring
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! V61308S Hoja de datos, Descripción, Manual

EM MICROELECTRONIC-MARIN SA
V6130
Accurate Power Surveillance and Software
Monitoring
Features
n Standby mode, maximum current 35 µA
n Reset output guaranteed for VDD voltage down to
1.2 V
n Comparator for voltage monitoring, voltage reference
1.17 V
n ±1.5% voltage reference accuracy at +25 °C
±3% voltage reference accuracy for -40 to +85 °C
n Programmable reset voltage monitoring
n Programmable power-on reset (POR) delay
n Watchdog with programmable time window
guarantees a minimum time and a maximum time
between software clearing of the watchdog
n Time base accuracy ±10%
n System enable (EN) output offers added security
n TTL/CMOS compatible
n -40 to +85 °C temperature range
n On request extended temperature range, -40 to
+125 °C
n DIP8 and SO8 packages
Typical Operating Configuration
Description
The V6130 offers a high level of integration by voltage
monitoring and software monitoring in an 8 lead pack-
age. A comparator monitors the voltage applied at the VIN
input comparing it with an internal 1.17 V reference. The
power-on reset function is initialized after VIN reaches 1.17
V and takes the reset output inactive after TPOR depending
of external resistance. The reset output goes active low
when the VIN voltage is less than 1.17 V. The RES and EN
outputs are guaranteed to be in a correct state for a sup-
ply voltage as low as 1.2 V. The watchdog function moni-
tors software cycle time and execution. If the software
clears the watchdog too quickly (incorrect cycle time) or
too slowly (incorrect execution) it will cause the system to
be reset. The system enable output prevents critical con-
trol functions being activated until software has success-
fully cleared the watchdog three times. Such a security
could be used to prevent motor controls being energized
on repeated resets of a faulty system.
Pin Assignment
Fig. 1
Applications
n Industrial electronics
n Cellular telephones
n Security systems
n Battery powered products
n Automotive electronics
Fig. 2
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V61308S pdf
Block Diagram
V6130
Fig. 8
Pin Description
Pin Name Function
1 EN
Push-pull active low enable output
2 RES Open drain active low reset output.
RES must be pulled up to VDD even
if unused
3 TCL
Watchdog timer clear input signal
4 VSS
5 NC
GND terminal
No connection
6 VDD
7R
8 VIN
Voltage supply
REXT input for RC oscillator tuning
Voltage comparator input
Table 5
Functional Description
VIN Monitoring
The power-on reset and the power-down reset are gener-
ated as a response to the external voltage level on the VIN
input. The external voltage level is typically obtained from
a voltage divider as shown in Fig. 9. The user defines an
external voltage divider to set the desired threshold level
for power-on reset and power-down reset in his system.
The internal comparator reference voltage is typically
1.17 V.
At power-up the reset output (RES) is held low (see Fig.
5). When VIN becomes greater than VREF, the RES output is
held low for an additional power-on reset (POR) delay
which is equal to the watchdog time TWD (typically 100 ms
with an external resistor of 118 kconnected at R pin).
The POR delay prevents repeated toggling of RES even if
VIN and the INPUT voltage drops out and recovers. The
POR delay allows the microprocessor’s crystal oscillator
time to start and stabilize and ensures correct recognition
of the reset signal to the microprocessor.
The RES output goes active low generating the
power-down reset whenever VIN falls below VREF. The sen-
sitivity or reaction time of the internal comparator to the
voltage level on VIN is typically 5 µs.
Timer Programming
The on-chip oscillator needs an external resistor REXT con-
nected between the R pin and VSS (see Fig. 9). It allows
the user to adjust the power-on reset (POR) delay, watch-
dog time TWD and with this also the closed and open time
windows as well as the watchdog reset pulse width
(TWD/40).
With REXT = 118 k, the typical delays are:
- Power-on reset delay: TPOR is 100 ms
- Watchdog time:
TWD is 100 ms
- Closed window:
TCW is 80 ms
- Open window:
TOW is 40 ms
- Watchdog reset:
TWDR is 2.5 ms
Note: The current consumption increases as the fre-
quency increases.
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a
“closed" window and an “open" window (see Fig.4) and is
defined by two parameters, TWD and the Open Window
Percentage (OWP).
The closed window starts just after the watchdog timer re-
sets and is defined by TCW = TWD - OWP(TWD).
The open window starts after the closed time window fin-
ishes and lasts till TWD + OWP(TWD). The open window
time is defined by TOW = 2 x OWP(TWD).
For example if TWD = 100 ms (actual value) and OWP =
±20% this means the closed window lasts during first the
80 ms (TCW = 80 ms = 100 ms - 0.2 (100 ms)) and the
open window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40
ms). The watchdog can be serviced between 80 ms and
120 ms after the timer reset. However as the time base is
±10% accurate, software must use the following calcula-
tion for servicing signal TCL during the open window:
Related to curves (Fig. 10 to Fig. 20), especially Fig. 19
and Fig. 20, the relation between TWD and REXT could
easily be defined. Let us take an example describing the
variations due to production and temperature:
1. Choice, TWD = 26 ms.
2. Related to Fig. 20, the coefficient (TWD to REXT) is 1.125
where REXT is in kand TWD in ms.
3. REXT (typ.) = 26 x 1.125 = 29.3 k.
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V61308S arduino
TWD Coefficient versus REXT at TA = +25°C
V6130
REXT Coefficient versus TWD at TA = +25°C
Fig. 19
Fig. 20
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