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Número de pieza V6118852F
Descripción 2/ 4 and 8 Multiplex LCD Driver
Fabricantes ETC 
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EM MICROELECTRONIC-MARIN SA
V6118
2, 4 and 8 Multiplex LCD Driver
Features
nV 6118 2 is 2 way multiplex with 2 rows and 38 columns
nV 6118 4 is 4 way multiplex with 4 rows and 36 columns
nV 6118 8 is 8 way multiplex with 8 rows and 32 columns
nLow dynamic current, 150 µA max.
nLow standby current, 1 µA max. at 25 oC
nVoltage bias and mux signal generation on chip
nDisplay refresh on chip, 40 x 8 RAM for display storage
nDisplay RAM addressable as 8, 40 bit words
nColumn driver only mode to have 40 column outputs
nCrossfree cascadable for large LCD applications
nSeparate logic and LCD supply voltage pins
nWide power supply range, VDD: 2 to 6 V, VLCD: 2 to 8 V
nBLANK function for LCD blanking on power up etc.
nVoltage bias inputs for applications with large pixel sizes
nBit mapped
nSerial input / output
nVery low external component count
n-40 oC to +85 oC temperature range
nNo busy states
nLCD updating synchronized to the LCD refresh signal
n QFP52 and TAB packages
Description
The V 6118 is a universal low multiplex LCD driver. The Ver-
sion V 6118 2 drives two ways multiplex (two blackplanes)
LCD, the version V 6118 4, four way multiplex LCD, and the
V 6118 8, eight way multiplex LCD. The display refresh is
handled on chip via a 40 x 8 bit RAM which holds the LCD
content driven by the driver. LCD pixels (or segments) are
addressed on a one to one basis with the 40 x 8 bit RAM ( a
set bit corresponds to an activated LCD pixel). The V 6118
has very low dynamic current consumption, 150 µA max.,
making it particularly attractive for portable and battery
powered applications. The wide operating range on both
the logic (VDD) and the LCD (VLCD) supply voltages offers
much application flexibility. The LCD bias generation is
internal. The voltage bias levels can also be provided extern-
nally for applications having large pixels sizes. The V 6118
can be used as a column only driver for cascading in large
display applications. In the column only mode, 40 column
Outputs available to address the display. A BLANK func-
tion is provided to blank the LCD, useful at power up to hold
the display blank until the microprocessor has updated the
display RAM.
Applications
nBalances and scales
nAutomotive displays
nUtility meters
nLarge displays (public information panels etc.)
nPagers
nPortable, battery operated products
nTelephones
Typical Operating Configuration
V6118 8
QFP52
V6118
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V6118852F pdf
V6118 2/4/8
X
40 bit display latch
40 display driver outputs
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V6118852F arduino
cascaded V 6118s are synchronized.Whencascading devices,
all STR lines must be tied together (see Fig. 10).
FR input
The FR signal controls the segment output frequency
generation (see Fig. 7,8 and 9). To avoid having DC on the
display, the FR signal must have a 50% duty cycle. The
frequency of the FR signal must be n times the desired display
refresh rate, where n is the V 6118 version no. (2,4 or 8). For
example, if the desired refresh rate is 40 Hz, the FR signal
frequency must be 320 Hz for the V6118 8. A selected row (on)
is in phasewith the FR signal (see Fig. 7, 8 and 9).
It is recommended that data transfer to the V 6118 should be
synchronized to the FR signal to avoid a falling or rising edge on
the FR signal while writing data to the V 6118. The LCD pixels
change polarity with the FR signal. On the edges of the FR
signal current spikes will appear on the VSS and VLCD supply
lines. If the supply lines have high impedance then voltage
spikes will appear. These voltage spikes could interfere with
data loading on the DI and CLK pins.
Driver output S1 to S40
There are 40 LCD driver outputs on the V 6118. When COL is
inactive the outputs S1 to Sn function as row drivers and the
outputs S(n + 1) to S40 function as column drivers, where n is
the V 6118 version no. (2,4 or 8). When COL is active, all 40
outputs function as column drivers (see table 6). There is a one
V6118 2/4/8
to one relationship between the display RAM and the LCD
driver outputs. Each pixel (segment) driven by the V 6118 on
the LCD has a display RAM bit which corresponds to it. Setting
the bit turns the segment "on" and clearing it turns it "off".
COL Input
The V 6118 functions as a row and column driver while the COL
is inactive. When active the COL input configures the V 6118 to
function as a column driver only. The former row outputs
function as column outputs. In cascaded applications one
V6118 should be used in the row column configuration (COL
inactive) and the rest as pure column drivers (COL active) (see
Fig. 10). Note when cascading V 6118s never cascades one
version with another. If a V6118 8 is used to drive the rows then
only V 6118 8s can be cascaded with it.When COL is active the
V 6118 needs 48 bits of data in a load cycle. 40 bits are used for
the column data and 8 bits to address the display RAM
regardless of V 6118 version (2, 4 or 8) (see Fig. 4, 5 and 10).
Power Up
On power up the data is shift registers, the display RAM and the
40-bit display latch are undefined. The STR input should be
taken high on power up to blank the display, and then the
display data written to the display RAM (see Fig. 11). When
finished the initial write to the display RAM, take the STR input
low to display the display RAM contents (see also section “STR
Input").
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