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PDF V58C2128164S Datasheet ( Hoja de datos )

Número de pieza V58C2128164S
Descripción HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo

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V58C2128164S Hoja de datos, Descripción, Manual
MOSEL VITELIC
V58C2128(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 128 Mbit DDR SDRAM
4 BANKS X 4Mbit X 8 (804)
4 BANKS X 2Mbit X 16 (164)
4 BANKS X 8Mbit X 4 (404)
Clock Cycle Time (tCK2)
Clock Cycle Time (tCK2.5)
System Frequency (fCK max)
6
DDR333B
7.5 ns
6 ns
167 MHz
7
DDR266A
7.5ns
7ns
143 MHz
PRELIMINARY
75
DDR266B
10 ns
7.5 ns
133 MHz
8
DDR200
10 ns
8 ns
125 MHz
Features
High speed data transfer rates with system
frequency up to 166 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 66-pin 400 mil TSOP
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-3-3 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2128(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 4Mbit x 8 (804),
4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4
(164). The V58C2128(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
CK Cycle Time (ns)
-6 -7 -75 -8
• • ••
Power
Std.
L
Temperature
Mark
Blank
V58C2128(804/404/164)S Rev.1.6 March 2002
1

1 page

V58C2128164S pdf
MOSEL VITELIC
V58C2128(804/404/164)S
Block Diagram
8M x 16
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 256
x 32 bit
Row decoder
Memory array
Bank 1
4096 x 256
x 32 bit
Row decoder
Memory array
Bank 2
4096 x 256
x 32 bit
Row decoder
Memory array
Bank 3
4096 x 256
x 32 bit
Input buffer Output buffer
Control logic & timing generator
CK, CK
DLL
DQ0-DQ15
DQS
Strobe
Gen.
Data Strobe
Capacitance*
TA = 0 to 70°C, VCC = 2.5V ± 0.2V, f = 1 Mhz
Input Capacitance
Symbol Min Max Unit
BA0, BA1, CKE, CS, RAS, (CAS,
A0-A11, WE)
CINI
2 3.0 pF
Input Capacitance (CK, CK)
Data & DQS I/O Capacitance
Input Capacitance (DM)
CIN2 2 3.0 pF
COUT 4 5 pF
CIN3 4 5.0 pF
*Note: Capacitance is sampled and not 100% tested.
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70 °C
Storage temperature range ................-55 to 150 °C
VDDSupply Voltage Relative to VSS.....-1V to +3.6V
VDDQ Supply Voltage Relative to VSS
......................................................-1V to +3.6V
VREF and Inputs Voltage Relative to VSS
......................................................-1V to +3.6V
I/O Pins Voltage Relative to VSS
.......................................... -0.5V to VDDQ+0.5V
Power dissipation .......................................... 1.6 W
Data out current (short circuit) ...................... 50 mA
*Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
V58C2128(804/404/164)S Rev. 1.6 March 2002
5

5 Page

V58C2128164S arduino
MOSEL VITELIC
V58C2128(804/404/164)S
Output Data and Data Strobe Valid Window for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T0 T1 T2 T3 T4
CK, CK
Command
READ
NOP
NOP
NOP
DQS
DQ
tDQSV(min)
D0 D1
tDV(min)
Read Preamble and Postamble Operation
Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read pream-
ble” (tRPRE). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of
valid data.
Once the burst of read data is concluded and given that no subsequent burst read operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “read postamble” (tRPST). This transition happens nominally one-half clock period after the last edge of
valid data.
Consecutive or “gapless” burst read operations are possible from the same DDR SDRAM device with no
requirement for a data strobe “read” preamble or postamble in between the groups of burst data. The data
strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the
data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles.
V58C2128(804/404/164)S Rev. 1.6 March 2002
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